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part number 440gx revision 1.01 ? november 1, 2004 amcc 1 440gx power pc 440gx embedded processor data sheet features ?powerpc ? 440 processor core operating up to 800mhz with 32kb i- and d-caches (with parity checking) ? on-chip 256kb sram configurable as l2 code store or ethernet packet store memory ? selectable processor:bus clock ratios (refer to the clocking chapter in the ppc440gx embedded processor user?s manual for details) ? double data rate ( ddr) synchronous dram (sdram) interface operating up to 166mhz ? external peripheral bus (32 bits) for up to eight devices with external mastering ? dma support for external peripherals, internal uart and memory ? pci-x v1.0a interface (32 or 64 bits, up to 133mhz) with support for conventional pci v2.3 ? two ethernet 10/100/1000mbps half- or full- duplex interfaces. operational modes supported are smii, gmii, rgmii, tbi and rtbi. ? tcp/ip acceleration hard ware (tah) provided for 10/100/1000 mbps ports that performs checksum processing, tcp segmentation, and includes support for jumbo frames ? two ethernet 10/100mbps half- or full-duplex interfaces. operational modes supported are mii, rmii, and smii. ? programmable interrupt controller supports interrupts from a variety of sources. ? i2o messaging unit for message transfer between the cpu and pci-x ? programmable general purpose timers (gpt) ? two serial ports (16750 compatible uart) ? two iic interfaces ? general purpose i/o (gpio) interface available ? jtag interface for board level testing ? processor can boot from pci memory ? available in ceramic and plastic packages description designed specifically to address high-end embedded applications, the powerpc 440gx (ppc440gx) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. this chip contains a high-performance risc processor core, ddr sdram controller, configurable 256kb sram to be used as l2 cache or software- controlled on-chip memory, pci-x bus interface, gigabit ethernet interfaces, tcp/ip acceleration hardware, i2o messaging unit, control for external rom and peripherals, dma with scatter-gather support, serial ports, iic interface, and general purpose i/o. technology: cmos cu-11, 0.13 m , 6-layer metal packages: 25mm, 552-ball ceramic ball grid array (cbga) or plastic ball grid array (pbga) power (estimated): less than: 4w typical @533mhz 5w typical @667mhz 6w typical @800mhz (estimated) supply voltages required: 3.3v, 2.5v, 1.5v
440gx ? power pc 440gx embedded processor 2 amcc revision 1.01 ? november 1, 2004 data sheet contents ordering and pvr information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 address maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 powerpc 440 processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 internal buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pci-x interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 ddr sdram memory controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 external peripheral bus controller (ebc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ethernet controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 serial port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 iic bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 general purpose timers (gpt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 general purpose io (gpio) controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 universal interrupt controller (uic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 plb performance monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 i2o messaging unit (imu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 signal lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 heat sink mounting information (ceramic package only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 spread spectrum clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 ddr sdram i/o specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ddr sdram write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ddr sdram read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
440gx ? power pc 440gx embedded processor amcc 3 revision 1.01 ? november 1, 2004 data sheet figures ppc440gx functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 25mm, 552-ball cbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 25mm, 552-ball fc-pbga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 heat sink attached with spring clip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 heat sink attached with adhesive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 input setup and hold waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 output delay and float timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ddr sdram signal termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ddr sdram write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ddr sdram memclkout0 and read clock delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ddr sdram read data path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ddr sdram read cycle timingexample 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ddr sdram read cycle timingexample 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ddr sdram read cycle timingexample 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 tables system memory address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 dcr address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 signals listed alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 signals listed by ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 pin summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 signal functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 package thermal specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 input capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 dc power supply loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 clocking specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 peripheral interface clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 i/o specificationsall speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 i/o specifications500mhzC800mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ddr sdram output driver specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 i/o timingddr sdram t ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 i/o timingddr sdram t sk , t sa , and t ha . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 i/o timingddr sdram t sd and t hd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 i/o timingddr sdram t sin and t din . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 strapping pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
440gx ? power pc 440gx embedded processor 4 amcc revision 1.01 ? november 1, 2004 data sheet ordering and pvr information for information on the availabilit y of the following parts, contac t your local am cc sales office. each part number contains a revision code. this is the die mask revision number and is included in the part number for identification purposes only. the pvr (processor version register) and the jtag id register are software accessible (read-only) and contain information that uniquely identifies the part. refer to the ppc440gx user?s manual for details on accessing these registers. order part number key product name order part number processor frequency package rev level pvr value jtag id ppc440gx ppc440gx-3cc533c 533mhz 25mm, 552 cbga c 0x51b21892 0x32054049 ppc440gx ppc440gx-3cc533e 533mhz 25mm, 552 cbga c 0x51b21892 0x32054049 ppc440gx PPC440GX-3CC667C 667mhz 25mm, 552 cbga c 0x51b21892 0x32054049 ppc440gx ppc440gx-3cc800c 800mhz 25mm, 552 cbga c 0x51b21892 0x32054049 ppc440gx ppc440gx-3fc533c 533mhz 25mm, 552 pbga c 0x51b21892 0x32054049 notes: 1. these part numbers are prototype parts that are intended for eval uation purposes only. only re vision level c parts are availa ble for pro- duction use. part number ppc440gx-3cc800ex package processor speed grade 3 reliability case temperature range revision level shipping package: blank = tray c = ceramic f = plastic c = -40c to +85c e = -40c to +105c
440gx ? power pc 440gx embedded processor amcc 5 revision 1.01 ? november 1, 2004 data sheet ppc440gx functional block diagram the ppc440gx is designed using the ibm ? microelectronics blue logic ? methodology in which major functional blocks are integrated together to create an applicat ion-specific product (asic). this approach provides a consistent way to create comp lex asics using ibm coreconnect bus ? architecture. note: ibm coreconnect buses provide: ? 128-bit plb interfaces up to 166.66mhz, 2.6gb/s on both the read and write data paths (5.2gb/s total) ? 32-bit opb interfaces up to 83.33mhz, 333mb/s address maps the ppc440gx incorporates two address maps. the first is a fixed processor system memory address map. this address map defines the possible contents of various address regions which the processor can access. the second address map is for device configuration registers (dcrs). the dcrs are accessed by software running on the ppc440gx processor through the use of mtdcr and mfdcr instructions. processor core dcr bus 32kb on-chip peripheral bus (opb) gpio iic uart dma bridge processor local bus (plb) ddr sdram external bus controller controller clock control reset power mgmt jtag trace timers mmu controller opb interrupt controller arb 32-bit addr 32-bit data 13-bit addr 32/64-bit data external bus master controller universal i-cache 32kb d-cache (4-channel) sram 256kb ppc440 63 internal 18 external pci-x bridge x2 x2 mal ethernet x2 dcrs 1 gmii or 2 rgmii or 1 tbi gp timers 1 mii or 2 rmii or zmii rgmii i2o messaging 83mhz max l2 controller 10/100 tah 10/100/ 1000 x2 133mhz max 166mhz max bridge bridge 32/64-bit data
440gx ? power pc 440gx embedded processor 6 amcc revision 1.01 ? november 1, 2004 data sheet system memory address map (part 1 of 2) function sub function start address end address size local memory 1 ddr sdram 0 0000 0000 0 7fff ffff 2gb sram 0 8000 0000 0 8000 3fff 256kb reserve 0 8000 4000 0 fffe ffff imu 0 ffff 0000 0 ffff ffff 64kb internal peripherals ebc 1 0000 0000 1 3fff ffff 1gb reserved 1 4000 0000 1 4000 01ff uart0 1 4000 0200 1 4000 0207 8b reserved 1 4000 0208 1 4000 02ff uart1 1 4000 0300 1 4000 0307 8b reserved 1 4000 0308 1 4000 03ff iic0 1 4000 0400 1 4000 041f 32b reserved 1 4000 0420 1 4000 04ff iic1 1 4000 0500 1 4000 051f 32b reserved 1 4000 0520 1 4000 05ff opb arbiter 1 4000 0600 1 4000 063f 64b reserved 1 4000 0640 1 4000 06ff gpio controller 1 4000 0700 1 4000 077f 128b ethernet phy zmii 1 4000 0780 1 4000 078f 16b ethernet phy gmii 1 4000 0790 1 4000 079f 16b reserved 1 4000 07a0 1 4000 07ff ethernet 0 controller 1 4000 0800 1 4000 08ff 256b ethernet 1 controller 1 4000 0900 1 4000 09ff 256b general purpose timer 1 4000 0a00 1 4000 0aff 256b tcpip accelerator 0 1 4000 0b00 1 4000 0bff 256b ethernet 2 controller 1 4000 0c00 1 4000 0cff 256b tcpip accelerator 1 1 4000 0d00 1 4000 0dff 256b ethernet 3 controller 1 4000 0e00 1 4000 0eff 256b reserved 1 4000 0f00 1 efff ffff expansion rom 2 1 f000 0000 1 ffdf ffff 254mb boot rom 2, 3 1 ffe0 0000 1 ffff ffff 2mb
440gx ? power pc 440gx embedded processor amcc 7 revision 1.01 ? november 1, 2004 data sheet pci-x reserved 2 0000 0000 2 07ff ffff pci-x i/o 2 0800 0000 2 0bff ffff 64mb reserved 2 0c00 0000 2 0ebf ffff pci-x external configuration re gisters 2 0ec0 0000 2 0ec0 0007 8b reserved 2 0ec0 0008 2 0ec7 ffff pci-x bridge core configuration r egisters 2 0ec8 0000 2 0ec8 00ff 256b reserved 2 0ec8 0100 2 0ec8 00ff pci-x special cycle 2 0ed0 0000 2 0edf ffff 1mb pci-x memory 2 0ee0 0000 f ffff ffff 55.76 gb notes: 1. ddr sdram and on-chip sram can be located anywhere in the local memory area of the memory map. 2. the boot rom and expansion rom areas of the memory map are intended for use by ro m or flash-type devic es. while locating volatile ddr sdram and sram in this region is supported, use of these regions for this purpose is not recommended. 3. when the optional boot from pci-x memory is selected, t he pci-x boot rom address space begins at 2 fffe 0000 (128 kb). system memory address map (part 2 of 2) function sub function start address end address size
440gx ? power pc 440gx embedded processor 8 amcc revision 1.01 ? november 1, 2004 data sheet dcr address map 4kb of device configuration registers function start address end address size total dcr address space 1 000 3ff 1kw (4kb) 1 by function: reserved 000 00b 12w clocking power on reset 00c 00d 2w system dcrs 00e 00f 2w memory controller 010 011 2w external bus controller 012 013 2w external bus master i/f 014 015 2w plb performance monitor 016 01f 10w sram 020 02f 16w l2 controller 030 03f 16w reserved 040 07f 64w plb 080 08f 16w plb to opb bridge out 090 09f 16w reserved 0a0 0a7 8w opb to plb bridge in 0a8 0af 8w power management 0b0 0b7 8w reserved 0b8 0bf 8w interrupt controller 0 0c0 0cf 16w interrupt controller 1 0d0 0df 16w clock, control, and reset 0e0 0ef 16w reserved 0f0 0ff 16w dma controller 100 13f 64w reserved 140 17f 64w ethernet mal 180 1ff 128w base interrupt controller 200 20f 16w interrupt controller 2 210 21f 16w reserved 220 3ff 480w notes: 1. dcr address space is addressable with up to 10 bits (1024 or 1k unique addresses). each unique address represen ts a single 32 -bit (word) register. one kiloword (1024w) equals 4kb (4096 bytes).
440gx ? power pc 440gx embedded processor amcc 9 revision 1.01 ? november 1, 2004 data sheet powerpc 440 processor core the powerpc 440 processor core is designed for high-end applications: raid controllers, san, iscsi, routers, switches, printers, set-top boxes, etc. it is the first processor core to implement the book e powerpc embedded architecture and the first to use the 128-bit vers ion of ibms on-chip coreconnect bus architecture. features include: ? up to 800mhz operation ? powerpc book e architecture ? 32kb i-cache, 32kb d-cache - utlb word wide parity on data and tag address parity with exception force ? three logical regions in d-cache: locked, transient, normal ? d-cache full line flush capability ? 41-bit virtual address, 36-bit (64gb) physical address ? superscalar, out-of-order execution ? 7-stage pipeline ? 3 execution pipelines ? dynamic branch prediction ? memory management unit - 64-entry, full associative, unified tlb with parity - separate instruction and data micro-tlbs - storage attributes for write-through, cache-inhibited, guarded, and big or little endian ? debug facilities - multiple instruction and data range breakpoints - data value compare - single step, branch, and trap events - non-invasive real-time trace interface ? 24 dsp instructions - single cycle multiply and multiply-accumulate - 32 x 32 integer multiply - 16 x 16 -> 32-bit mac internal buses the powerpc 440gx features three ibm standard on-chi p buses: the processor local bus (plb), the on-chip peripheral bus (opb), and the device control register bus (dcr). the high performance, high bandwidth cores such as the powerpc 440 processor core, the ddr sdram memory controller, and the pci-x bridge connect to the plb. the opb hosts lower data rate peripherals. the daisy-chained dcr provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores. features include: ?plb - 128-bit implementation of the plb architecture - separate and simultaneous read and write data paths - 64-bit address - simultaneous control, address, and data phases - four levels of pipelining - byte enable capability suppo rting unaligned transfers
440gx ? power pc 440gx embedded processor 10 amcc revision 1.01 ? november 1, 2004 data sheet - 32- and 64-byte burst transfers - 166mhz, maximum 5.2gb/s (simultaneous read and write) - processor:bus clock ratios of n:1 and n:2 ?opb - dynamic bus sizing 32-, 16-, and 8-bit data path - 36-bit address - 83.33mhz, maximum 333mb/s ? dcr - 32-bit data path - 10 bit address on-chip sram features include: ? four banks of 64kb each for a total of 256kb ? configurable as either code (l2) cache or software-controlled on-chip memory, or sram ? memory cycles supported: - single beat read and write, 1 to 16 bytes - 32- and 64-byte burst transfers - guarded memory accesses ? sustainable 2.6gb/s peak bandwidth at 166mhz ? use as an l2 cache improves proces sor performance and reduces the plb load - cache coherency maintained by a hardware snoop mechanism or software - data array and tag array parity - unified data and instruction cache - 4-way set associative - 36-bit addressing - full lru replacement algorithm - write through, look aside ? use as ethernet packet store allows ethernet packets to be held for processing by the tah unit pci-x interface the pci-x interface allows connection of pci and pci-x devices to the powerpc processor and local memory. this interface is designed to version 1.0a of the pci-x sp ecification and supports 32- and 64-bit pci-x buses. pci 32/64-bit conventional mode, compatible with pci version 2.3, is also supported. reference specifications: ? powerpc coreconnect bus (plb) specification version 3.1 ? pci specification version 2.3 ? pci bus power management interface specification version 1.1 features include: ? pci-x 1.0a - split transactions - frequency to 133mhz - 32- and 64-bit bus
440gx ? power pc 440gx embedded processor amcc 11 revision 1.01 ? november 1, 2004 data sheet ? pci 2.3 backward compatibility - frequency to 66mhz - 32- and 64-bit bus ? can be the pci host bus bridge or an adapter device's pci interface ? internal pci arbitration function, supporting up to six ex ternal devices, that can be disabled for use with an external arbiter ? support for message signaled interrupts ? simple message pa ssing capability ? asynchronous to the plb ? pci power management 1.1 ? pci register set addressable both from on-chip processor and pci device sides ? ability to boot from pci-x bus memory ? error tracking/status ? supports initiation of transfer to the following address spaces: - single beat i/o reads and writes - single beat and burst memory reads and writes - single beat configuration reads and writes (type 0 and type 1) - single beat special cycles ddr sdram memory controller the double data rate (ddr) sdram memory controller supports industry standard 184-pin dimms, so-dimms, and other discrete devices. up to four 512mb logical banks are supported in limited configurations. global memory timings, address and bank sizes, and me mory addressing modes are programmable. features include: ? registered and non-registered industry standard dimms ? 64-bit memory interface with optional 8-bit ecc (sec/ded) ? sustainable 2.6gb/s peak bandwidth at 166mhz ? sstl_2 logic ? 1 to 4 chip selects ? cas latencies of 2, 2.5 and 3 supported ? ddr200/266/333 support ? page mode accesses (up to eight open pages) with configurable paging policy ? programmable address mapping and timing ? hardware and software initiated self-refresh ? power management (self-refresh, suspend, sleep) external peripheral b us controller (ebc) features include: ? up to eight rom, eprom, sram, flash memory , and slave peripheral i/o banks supported ? up to 83.33mhz operation (333mb/s) ? burst and non-burst devices ? 8-, 16-, 32-bit byte-addressable data bus ? 32-bit address, 4gb address space ? peripheral device pacing with external ready
440gx ? power pc 440gx embedded processor 12 amcc revision 1.01 ? november 1, 2004 data sheet ? latch data on ready, synchronous or asynchronous ? programmable access timing per device - 256 wait states for non-burst - 32 burst wait states for first access and up to 8 wait states for subsequent accesses - programmable cson, csoff relative to address - programmable oeon, weon, weoff (1 to 4 clock cycles) relative to cs ? programmable address mapping ? external dma slave support ? external master interface - write posting from external master - read prefetching on plb for external master reads - bursting capable from external master - allows external master access to all non-ebc plb slaves - external master can control ebc slaves for own access and control ethernet contro ller interface ethernet support provided by the ppc440gx interfaces to the physical layer, but the phy is not included on the chip. features include: ? one to four 10/100 interfaces running in full- and half-duplex modes - one full media independent interface (mii) with 4-bit parallel data transfer - two reduced media independent interfaces (rmii) with 2-bit parallel data transfer - four serial media independent interfaces (smii) ? one or two gmii interfaces running in full- and half-duplex modes at 10mb/s or 100mb/s or 1000mb/s - one full gigabit media independent interface (gmii) with 8-bit parallel data transfer - two reduced gigabit media independent interfaces (rgmii) with 4-bit parallel data transfer ? one or two tbi interfaces running in full- and half-duplex modes at 10mb/s or 100mb/s or 1000mb/s - one full ten bit interface (tbi) with 10-bit parallel data transfer - two reduced ten bit interfaces (rtbi) with 4-bit parallel data transfer ? jumbo frame support (9016 byte) - support for ethernet ii formatted frames (rfc894) - support for ieee form atted frames (rfc1042) - handles vlan-tagged frames tcp/ip acceleration hardware (tah) features include: ? offloads gigabit ethernet protocol processing from the cpu ? checksum verification for tcp/udp/ip headers in the receive path ? checksum generation for tcp/udp/ip headers in the transmit path ? tcp segmentation support in the transmit path
440gx ? power pc 440gx embedded processor amcc 13 revision 1.01 ? november 1, 2004 data sheet dma controller features include: ? supports the following transfers: - memory-to-memory transfers - buffered peripheral to memory transfers - buffered memory to peripheral transfers ? four channels ? scatter/gather capability for prog ramming multiple dma operations ? 8-, 16-, 32-bit peripheral support (opb and external) ? 64-bit addressing ? 128 byte fifo buffer ? address increment or decrement ? supports internal and external peripherals ? support for memory mapped peripherals ? support for peripherals running on slower frequency buses serial port features include: ? one 8-pin uart and one 4-pin uart interface provided ? selectable internal or external serial clock to allow wide range of baud rates ? register compatibility with 16750 register set ? complete status re porting capability ? fully programmable serial-interface characteristics ? supports dma using internal dma engine iic bus interface features include: ? two iic interfaces provided ? support for philips? semiconductors i 2 c specification, dated 1995 ? operation at 100khz or 400khz ?8-bit data ? 10- or 7-bit address ? slave transmitter and receiver ? master transmitter and receiver ? multiple bus masters ? supports fixed v dd iic interface ? two independent 4 x 1 byte data buffers ? twelve memory-mapped, fully programmable configuration registers ? one programmable interrupt request signal ? provides full management of all iic bus protocols ? programmable error recovery
440gx ? power pc 440gx embedded processor 14 amcc revision 1.01 ? november 1, 2004 data sheet general purpose timers (gpt) provides a separate time base counter and additional system timers in addition to those defined in the processor core. ? 32-bit time base counter driven by the opb bus clock ? seven 32-bit compare timers general purpose io (gpio) controller ? controller functions and gpio registers are programm ed and accessed via memory-mapped opb bus master accesses. ? the 32 gpios are pin-shared with other functions. dcrs control whether a particular pin that has gpio capabilities acts as a gpio or is used for another purpose. ? each gpio output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1). universal interrupt controller (uic) four universal interrupt controllers (uic) are available. they provide control, status, and communications necessary between the external and internal source s of interrupts and the on-chip powerpc processor. note: processor specific interrupts (for example, page faults) do not use uic resources. features include: ? 18 external interrupts ? 63 internal interrupts ? edge triggered or level-sensitive ? positive or negative active ? non-critical or critical interrupt to the on-chip processor core ? programmable interrupt priority ordering ? programmable critical interrupt vector for faster vector processing plb performance monitor the plb performance monitor (ppm) provides hardwa re for counting certain events associated with plb transactions. the contents of the counters can be read by software for analysis and enhancement of plb performance, or software debug. the data includes identification and duration of the events. i2o messaging unit (imu) the imu interfaces to the plb as a master or slave and allows messages to be transferred between two plb masters (for example, the 440 cpu and pci-x). features include: ? three messaging methods - 4 message registers2 inbound, 2 outbound - 2 doorbell registers1 inbound, 1 outbound - 4 circular queues2 inbound, 2 outbound ? up to 7 different interrupt outputs generated ? support for interrupt masking
440gx ? power pc 440gx embedded processor amcc 15 revision 1.01 ? november 1, 2004 data sheet jtag features include: ? ieee 1149.1 test access port ? ibm riscwatch debugger support ? jtag boundary scan description language (bsdl)
440gx ? power pc 440gx embedded processor 16 amcc revision 1.01 ? november 1, 2004 data sheet 25mm, 552-ball cbga package top view bottom view note: all dimensions are in mm. a1 corner 135 7 911131517 19 2 4 6 810 12 14 16 18 21 23 20 22 24 a b c d e f g h j k l m aa n p r t u v w y ab ac ad 25.0 0.2 1.00 typ 25.0 0.2 0.8 0.04 solderball x 552 23.0 capacitor 8.4 chip 2.31 max 1.89 min 3.977 max 0.71 min 0.81 max 0.779 min 0.857 max 3.379 min
440gx ? power pc 440gx embedded processor amcc 17 revision 1.01 ? november 1, 2004 data sheet 25mm, 552-ball fc-pbga package top view bottom view note: all dimensions are in mm. a1 corner 135 7 911131517 19 2 4 6 810 12 14 16 18 21 23 20 22 24 a b c d e f g h j k l m aa n p r t u v w y ab ac ad 25.0 1.00 typ 25.0 0.66 0.1 solderball x 552 23.0 7.5 0.5 0.1 3.191 0.17 1.214 ref 1 0.3 0.508 ref 24 ad a 1 23.0
440gx ? power pc 440gx embedded processor 18 amcc revision 1.01 ? november 1, 2004 data sheet signal lists the following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. multiplexed signals are show n with the default signal (following reset) not in brackets and the alternate signal in brackets. multiplexed signals appear al phabetically multiple times in the listonce for each signal name on the ball. the page number listed gives the page in signal functional description on page 50 where the signals in the indicated interface group begin. in cases where signals in the same interface group (for example, ethernet) have different names to distinguish variations in the mode of operation, the names are separated by a comma with the primary name appearing first. these signals are listed only once, and appear alphabetically by the primary name. signals listed alphabetically (part 1 of 24) signal name ball interface group page agnd j01 poweranalog ground 57 agnd j24 agnd aa11 amv dd ab11 powermemclkout pll analog voltage 57 apv dd g01 powerpci-x pll analog voltage 57 asv dd g24 powersysclk pll analog voltage 57 ba0 aa16 ddr sdram 51 ba1 ad09 banksel0 ab15 ddr sdram 51 banksel1 w14 banksel2 ad11 banksel3 ad05 [be0 ]pcixc0 f14 pci-x 50 [be1 ]pcixc1 e16 [be2 ]pcixc2 c19 [be3 ]pcixc3 f20 [be4 ]pcixc4 c08 [be5 ]pcixc5 c03 [be6 ]pcixc6 g09 [be7 ]pcixc7 f09 busreq[trcts1] aa24 external master peripheral 54 cas ab05 ddr sdram 51 clken0 ad17 ddr sdram 51 clken1 ab10 clken2 y09 clken3 w09
440gx ? power pc 440gx embedded processor amcc 19 revision 1.01 ? november 1, 2004 data sheet dm0 t16 ddr sdram 51 dm1 aa18 dm2 ab14 dm3 p13 dm4 aa09 dm5 aa07 dm6 y03 dm7 v03 dm8 ac05 dmaack0 n05 external slave peripheral 53 dmaack1 p07 dmaack2[gmcrxd0, gmc0rxd0, tbirxd0, rtbi0rxd0] p06 dmaack3[gmcrxd1, gmc0rxd1, tbirxd1, rtbi0rxd1] p11 dmareq0 r03 external slave peripheral 53 dmareq1 m11 dmareq2[gmcrxdv, gmc0rxctl, tbirxd8, rtbi0rxd4] n11 dmareq3[gmctxen, gmc0txctl, tbitxd8, rtbi0txd4] p01 dqs0 ac20 ddr sdram 51 dqs1 ac16 dqs2 ac14 dqs3 ab13 dqs4 ac11 dqs5 ac09 dqs6 y04 dqs7 t01 dqs8 aa05 drvrinh2 a05 system 56 signals listed alphabetically (part 2 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 20 amcc revision 1.01 ? november 1, 2004 data sheet ecc0 ab07 ddr sdram 51 ecc1 ab06 ecc2 ad06 ecc3 w07 ecc4 u09 ecc5 ac03 ecc6 ab04 ecc7 ad04 emccd, emc1rxerr, gmcgtxclk, gmc0txclk, tbitxclk, rtbi0txclk j07 ethernet 51 emccrs, emc0crsdv, gmctxd7, gmc1txd3, tbitxd7, rtbi1txd3 k07 ethernet 51 emcmdclk j08 ethernet 51 emcmdio l05 ethernet 51 emcrxclk, gmctxd5, gmc1txd1, tbitxd5, rtbi1txd1 j02 ethernet 51 emcrxd0, emc0rxd0, emc0rxd g03 ethernet 51 emcrxd1, emc0rxd1, emc1rxd e01 emcrxd2, emc1rxd0, emc2rxd, gmctxd0, gmc0txd0, tbitxd0, rtbi0txd0 a07 emcrxd3, emc1rxd1, emc3rxd gmctxd1, gmc0txd1, tbitxd1, rtbi0txd1 h09 emcrxdv, emc1crsdv, gmctxd4, gmc1txd0, tbitxd4, rtbi1txd0 k01 ethernet 51 emcrxerr, emc0rxerr, gmctxd6, gmc1txd2, tbitxd6, rtbi1txd2 k03 ethernet 51 emctxclk, emcrefclk j06 ethernet 51 emctxd0, emc0txd0, emc0txd l09 ethernet 51 emctxd1, emc0txd1, emc1txd k05 emctxd2, emc1txd0, emc2txd, gmctxd2, gmc0txd2, tbitxd2, rtbi0txd2 j04 emctxd3, emc1txd1, emc3txd, gmctxd3, gmc0txd3, tbitxd3, rtbi0txd3 j03 emctxen, emc0txen, emcsync l06 ethernet 51 emctxerr, emc1txen, gmcrxclk, gmc0rxclk, tbirxclk0, rtbi0rxclk c05 ethernet 51 signals listed alphabetically (part 3 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 21 revision 1.01 ? november 1, 2004 data sheet eot0/tc0 r16 external slave peripheral 53 eot1/tc1 p15 eot2/tc2[gmcrxd2, gmc0rxd2, tbirxd2, rtbi0rxd2] p16 eot3/tc3[gmcrxd3, gmc0rxd3, tbirxd3, rtbi0rxd3] m16 extack [trcts2] aa22 external master peripheral 54 extreq [trcts3] ab23 external master peripheral 54 extreset t17 external mast er peripheral 54 [gmccd, gmc1rxclk, rtbi1rxclk]trcts1[gpio27] p03 ethernet 51 [gmccrs, gmc1txclk, rtbi1txclk]trcts6 r01 ethernet 51 gmcrefclk l01 ethernet 51 [gmcrxd0, gmc0rxd0, tbirxd0, rtbi0rxd0]dmaack2 p06 ethernet 51 [gmcrxd1, gmc0rxd1, tbirxd1, rtbi0rxd1]dmaack3 p11 [gmcrxd2, gmc0rxd2, tbirxd2, rtbi0rxd2]eot2/tc2 p16 [gmcrxd3, gmc0rxd3, tbirxd3, rtbi0rxd3]eot3/tc3 m16 [gmcrxd4, gmc1rxd0, tbirxd4, rtbi1rxd0][gpio28]trcts2 r07 [gmcrxd5, gmc1rxd1, tbirxd5, rtbi1rxd1][gpio29]trcts3 p09 [gmcrxd6, gmc1rxd2, tbirxd6, rtbi1rxd2][gpio30]trcts4 r09 [gmcrxd7, gmc1rxd3, tbirxd7, rtbi1rxd3][gpio31]trcts5 t06 [gmcrxdv, gmc0rxctl, tbirxd8, rtbi0rxd4]dmareq2 n11 ethernet 51 gmcrxer, gmc1rxctl, tbirxd9, rtbi1rxd4 p04 ethernet 51 gmctxer, gmc1txctl, tbitxd9, rtbi1txd4 l07 ethernet note: used as initialization strapping input. 51 [gmctxen, gmc0txctl, tbitxd8, rtbi0txd4]dmareq3 p01 ethernet 51 [gmctxclk, tbirxclk1]gpio11 p14 ethernet 51 signals listed alphabetically (part 4 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 22 amcc revision 1.01 ? november 1, 2004 data sheet gnd b06 power 57 gnd b10 gnd b13 gnd b17 gnd b21 gnd d04 gnd d08 gnd d12 gnd d15 gnd d19 gnd d23 gnd f02 gnd f06 gnd f10 gnd f13 gnd f17 gnd f21 gnd h04 gnd h08 gnd h12 gnd h15 gnd h19 gnd h23 gnd k02 gnd k06 gnd k10 gnd k13 gnd k17 gnd k21 gnd m04 signals listed alphabetically (part 5 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 23 revision 1.01 ? november 1, 2004 data sheet gnd m08 power 57 gnd m12 gnd m15 gnd m19 gnd m23 gnd n02 gnd n06 gnd n10 gnd n13 gnd n17 gnd n21 gnd r04 gnd r08 gnd r12 gnd r15 gnd r19 gnd r23 gnd u02 gnd u06 gnd u10 gnd u13 gnd u17 gnd u21 gnd w04 gnd w08 gnd w12 gnd w15 gnd w19 gnd w23 signals listed alphabetically (part 6 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 24 amcc revision 1.01 ? november 1, 2004 data sheet gnd aa02 power 57 gnd aa06 gnd aa10 gnd aa13 gnd aa17 gnd aa21 gnd ac04 gnd ac08 gnd ac12 gnd ac15 gnd ac19 signals listed alphabetically (part 7 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 25 revision 1.01 ? november 1, 2004 data sheet [gpio00]irq00 n18 system 56 [gpio01]irq01 l20 [gpio02]irq02 p20 [gpio03]irq03 l18 [gpio04]irq04 n14 [gpio05]irq05 m20 [gpio06]irq06 m14 [gpio07]irq07 p18 [gpio08]irq08 n20 [gpio09]irq09 p22 [gpio10]irq10 v18 gpio11[gmctxclk, tbirxclk1] p14 [gpio12]uart1_rx c18 [gpio13]uart1_tx j16 [gpio14]uart1_dsr/cts g06 [gpio15]uart1_rts/dtr e05 [gpio16]iic1sclk h11 [gpio17]iic1sda h14 [gpio18]trcbs0[irq13] n16 [gpio19]trcbs1[irq14] p17 [gpio20]trcbs2[irq15] t20 [gpio21]trces0[irq16] t21 [gpio22]trces1[irq17] p23 [gpio23]trces2 n09 [gpio24]trces3 p08 [gpio25]trces4 t05 [gpio26]trcts0 t04 [gpio27]trcts1[gmccd, gmc1rxclk, rtbi1rxclk] p03 [gpio28]trcts2[gmcrxd4, gmc1rxd0, tbirxd4, rtbi1rxd0] r07 [gpio29]trcts3[gmcrxd5, gmc1rxd1, tbirxd5, rtbi1rxd1] p09 [gpio30]trcts4[gmcrxd6, gmc1rxd2, tbirxd6, rtbi1rxd2] r09 [gpio31]trcts5[gmcrxd7, gmc1rxd3, tbirxd7, rtbi1rxd3] t06 signals listed alphabetically (part 8 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 26 amcc revision 1.01 ? november 1, 2004 data sheet halt v05 system 56 holdack[trcts4] y21 exter nal master peripheral 54 holdreq[trcts5] y23 exter nal master peripheral 54 iic0sclk g11 iic peripheral 55 iic0sda g13 iic peripheral 55 iic1sclk[gpio16] h11 iic peripheral 55 iic1sda[gpio17] h14 iic peripheral 55 irq00[gpio00] n18 interrupts 55 irq01[gpio01] l20 irq02[gpio02] p20 irq03[gpio03] l18 irq04[gpio04] n14 irq05[gpio05] m20 irq06[gpio06] m14 irq07[gpio07] p18 irq08[gpio08] n20 irq09[gpio09] p22 irq10[gpio10] v18 [irq11]pcireq1 e21 [irq12]pcignt1 c22 [irq13][gpio18]trcbs0 n16 [irq14][gpio19]trcbs1 p17 [irq15][gpio20]trcbs2 t20 [irq16][gpio21]trces0 t21 [irq17][gpio22]trces1 p23 signals listed alphabetically (part 9 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 27 revision 1.01 ? november 1, 2004 data sheet memaddr00 y19 ddr sdram 51 memaddr01 ad20 memaddr02 y20 memaddr03 ab20 memaddr04 ad18 memaddr05 ad16 memaddr06 ab18 memaddr07 y14 memaddr08 v13 memaddr09 v11 memaddr10 w16 memaddr11 y11 memaddr12 v10 memclkout0 v09 ddr sdram 51 memclkout0 v08 signals listed alphabetically (part 10 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 28 amcc revision 1.01 ? november 1, 2004 data sheet memdata00 ad21 ddr sdram 51 memdata01 ab21 memdata02 ac22 memdata03 aa20 memdata04 u16 memdata05 v17 memdata06 ad19 memdata07 ab19 memdata08 w18 memdata09 v16 memdata10 y17 memdata11 ab16 memdata12 ac18 memdata13 y18 memdata14 r14 memdata15 ab17 memdata16 aa14 memdata17 ad15 memdata18 t15 memdata19 v15 memdata20 y16 memdata21 u14 memdata22 t13 memdata23 y15 memdata24 ad13 memdata25 ad14 memdata26 v14 memdata27 y13 memdata28 p12 memdata29 ab12 memdata30 y12 memdata31 v12 signals listed alphabetically (part 11 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 29 revision 1.01 ? november 1, 2004 data sheet memdata32 w11 ddr sdram 51 memdata33 ad12 memdata34 y10 memdata35 t12 memdata36 u11 memdata37 t11 memdata38 t10 memdata39 ad10 memdata40 ab08 memdata41 ad08 memdata42 r11 memdata43 y07 memdata44 ac07 memdata45 ab09 memdata46 y06 memdata47 y08 memdata48 aa01 memdata49 aa03 memdata50 ab02 memdata51 y01 memdata52 ab03 memdata53 y02 memdata54 v07 memdata55 v01 memdata56 t08 memdata57 u07 memdata58 w01 memdata59 w03 memdata60 v06 memdata61 t07 memdata62 w05 memdata63 u05 memvref1 t14 ddr sdram 51 memvref2 t09 signals listed alphabetically (part 12 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 30 amcc revision 1.01 ? november 1, 2004 data sheet no ball a01 a physical ball does not exist at these ball coordinates. na no ball a02 no ball a03 no ball a22 no ball a23 no ball a24 no ball b01 no ball b02 no ball b23 no ball b24 no ball c01 no ball c24 no ball ab01 no ball ab24 no ball ac01 no ball ac02 no ball ac23 no ball ac24 no ball ad01 no ball ad02 no ball ad03 no ball ad22 no ball ad23 no ball ad24 signals listed alphabetically (part 13 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 31 revision 1.01 ? november 1, 2004 data sheet ov dd b04 power 57 ov dd b12 ov dd b19 ov dd d02 ov dd d10 ov dd d17 ov dd f08 ov dd f15 ov dd f23 ov dd h06 ov dd h10 ov dd h13 ov dd h21 ov dd k04 ov dd k08 ov dd k19 ov dd m02 ov dd m17 ov dd n08 ov dd n23 ov dd r06 ov dd r17 ov dd r21 ov dd u04 ov dd u19 ov dd w02 ov dd aa23 pcix133cap g08 pci-x 50 pcixack64 d09 pci-x 50 signals listed alphabetically (part 14 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 32 amcc revision 1.01 ? november 1, 2004 data sheet pcixad00 c17 pci-x 50 pcixad01 b09 pcixad02 g10 pcixad03 e10 pcixad04 c10 pcixad05 a10 pcixad06 f11 pcixad07 g12 pcixad08 g14 pcixad09 a15 pcixad10 c15 pcixad11 e15 pcixad12 g15 pcixad13 b16 pcixad14 c16 pcixad15 d16 pcixad16 e18 pcixad17 e19 pcixad18 f18 pcixad19 g18 pcixad20 d20 pcixad21 a20 pcixad22 a21 pcixad23 c21 pcixad24 f22 pcixad25 b22 pcixad26 g21 pcixad27 e23 pcixad28 c23 pcixad29 f24 pcixad30 d22 pcixad31 d24 signals listed alphabetically (part 15 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 33 revision 1.01 ? november 1, 2004 data sheet pcixad32 h03 pci-x 50 pcixad33 h01 pcixad34 l08 pcixad35 f01 pcixad36 d01 pcixad37 j05 pcixad38 h05 pcixad39 g02 pcixad40 e02 pcixad41 c02 pcixad42 a08 pcixad43 g05 pcixad44 f03 pcixad45 d03 pcixad46 b03 pcixad47 h07 pcixad48 g04 pcixad49 e04 pcixad50 c04 pcixad51 a04 pcixad52 f05 pcixad53 d05 pcixad54 b05 pcixad55 c09 pcixad56 e06 pcixad57 c06 pcixad58 a06 pcixad59 f07 pcixad60 e07 pcixad61 d07 pcixad62 b07 pcixad63 e08 signals listed alphabetically (part 16 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 34 amcc revision 1.01 ? november 1, 2004 data sheet pcixc0[be0 ]f14 pci-x 50 pcixc1[be1 ]e16 pcixc2[be2 ]c19 pcixc3[be3 ]f20 pcixc4[be4 ]c08 pcixc5[be5 ]c03 pcixc6[be6 ]g09 pcixc7[be7 ]f09 pcixcap l23 pci-x 50 pcixclk e03 pci-x 50 pcixdevsel e13 pci-x 50 pcixframe a11 pci-x 50 pcixgnt0 e22 pci-x 50 pcixgnt1 [irq12] c22 pcixgnt2 n22 pcixgnt3 m18 pcixgnt4 r22 pcixgnt5 p19 pcixidsel g07 pci-x 50 pcixint m07 pci-x 50 pcixirdy e12 pci-x 50 pcixm66en a14 pci-x 50 pcixparhigh l04 pci-x 50 pcixparlow f16 pci-x 50 pcixperr a17 pci-x 50 pcixreq0 e24 pci-x 50 pcixreq1 [irq11] e21 pcixreq2 e20 pcixreq3 r20 pcixreq4 g23 pcixreq5 r18 pcixreq64 e09 pci-x 50 pcixreset m24 pci-x 50 pcixserr a18 pci-x 50 signals listed alphabetically (part 17 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 35 revision 1.01 ? november 1, 2004 data sheet pcixstop l12 pci-x 50 pcixtrdy c12 pci-x 50 peraddr00 d11 external slave peripheral note: peraddr00 is the most significant bit (msb) on this bus. 53 peraddr01 c11 peraddr02 b11 peraddr03 a12 peraddr04 a19 peraddr05 d18 peraddr06 e11 peraddr07 m03 peraddr08 n01 peraddr09 e14 peraddr10 c20 peraddr11 a16 peraddr12 a13 peraddr13 b14 peraddr14 c14 peraddr15 d14 peraddr16 b20 peraddr17 l15 peraddr18 l21 peraddr19 l22 peraddr20 m22 peraddr21 m01 peraddr22 l24 peraddr23 p24 peraddr24 t19 peraddr25 r24 peraddr26 u22 peraddr27 u24 peraddr28 n03 peraddr29 v20 peraddr30 v23 peraddr31 v21 signals listed alphabetically (part 18 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 36 amcc revision 1.01 ? november 1, 2004 data sheet perblast c07 external slave peripheral 53 perclk u18 external master peripheral 54 percs0 e17 external slave peripheral 53 percs1 l10 percs2 v04 percs3 t24 percs4 l03 percs5 t03 percs6 l13 percs7 u03 signals listed alphabetically (part 19 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 37 revision 1.01 ? november 1, 2004 data sheet perdata00 h24 external slave peripheral note: perdata00 is the most significant bit (msb) on this bus. 53 perdata01 h22 perdata02 h20 perdata03 g20 perdata04 g19 perdata05 h18 perdata06 j23 perdata07 j22 perdata08 j21 perdata09 j20 perdata10 j19 perdata11 j18 perdata12 j17 perdata13 j15 perdata14 j14 perdata15 j13 perdata16 j12 perdata17 j11 perdata18 j10 perdata19 j09 perdata20 l14 perdata21 k24 perdata22 k22 perdata23 k20 perdata24 k18 perdata25 k16 perdata26 k14 perdata27 k11 perdata28 k09 perdata29 l19 perdata30 l17 perdata31 l16 [pererr]trcts6 p21 exter nal master peripheral 54 peroe m09 external slave peripheral 53 signals listed alphabetically (part 20 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 38 amcc revision 1.01 ? november 1, 2004 data sheet perpar0 t23 external slave peripheral 53 perpar1 t22 perpar2 w20 perpar3 u20 perready[rcvrinh] n07 external slave peripheral 53 perr/w p05 external slave peripheral 53 perwbe0 t18 external slave peripheral 53 perwbe1 v19 perwbe2 w22 perwbe3 w24 perwe p02 external slave peripheral 53 ras ad07 ddr sdram 51 [rcvrinh]perready n07 system 56 refven l02 system 56 sv dd u12 power 57 sv dd u15 sv dd w10 sv dd w17 sv dd aa08 sv dd aa15 sv dd ac06 sv dd ac13 sv dd ac21 sysclk g22 system 56 syserr t02 system 56 sysreset p10 system 56 tck v22 jtag 55 tdi y24 jtag 55 tdo y22 jtag 55 testen m05 system 56 tmrclk u01 system 56 tms ab22 jtag 55 signals listed alphabetically (part 21 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 39 revision 1.01 ? november 1, 2004 data sheet trcbs0[gpio18][irq13] n16 trace 57 trcbs1[gpio19][irq14] p17 trcbs2[gpio20][irq15] t20 trcclk r05 trace 57 trces0[gpio21][irq16] t21 trace 57 trces1[gpio22][irq17] p23 trces2[gpio23] n09 trces3[gpio24] p08 trces4[gpio25] t05 trcts0[gpio26] t04 trace 57 trcts1[gpio27][gmccd, gmc1rxclk, rtbi1rxclk] p03 trace 57 [trcts1]busreq aa24 trace 57 trcts2[gpio28][gmcrxd4, gmc1rxd0, tbirxd4, rtbi1rxd0] r07 trace 57 [trcts2]extack aa22 trace 57 trcts3[gpio29][gmcrxd5, gmc1rxd1, tbirxd5, rtbi1rxd1] p09 trace 57 [trcts3]extreq ab23 trace 57 trcts4[gpio30][gmcrxd6, gmc1rxd2, tbirxd6, rtbi1rxd2] r09 trace 57 [trcts4]holdack y21 trace 57 trcts5[gpio31][gmcrxd7, gmc1rxd3, tbirxd7, rtbi1rxd3] t06 trace 57 [trcts5]holdreq y23 trace 57 trcts6[gmccrs, gmc1txclk, rtbi1txclk] r01 trace 57 trcts6[pererr] p21 trace 57 trst n24 jtag 55 uart0_cts c13 uart peripheral 54 uart0_dcd v24 uart peripheral note: used as initialization strapping input. 54 uart0_dsr v02 uart peripheral note: used as initialization strapping input. 54 uart0_dtr b18 uart peripheral 54 uart0_ri h16 uart peripheral 54 uart0_rts g16 uart peripheral 54 uart0_rx g17 uart peripheral 54 signals listed alphabetically (part 22 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 40 amcc revision 1.01 ? november 1, 2004 data sheet uart0_tx l11 uart peripheral 54 uart1_dsr/cts [gpio14] g06 uart peripheral 54 uart1_rts/dtr [gpio15] e05 uart peripheral 54 uart1_rx[gpio12] c18 uart peripheral 54 uart1_tx[gpio13] j16 uart peripheral 54 uartserclk a09 uart peripheral 54 v dd b08 power 57 v dd b15 v dd d06 v dd d13 v dd d21 v dd f04 v dd f12 v dd f19 v dd h02 v dd h17 v dd k12 v dd k15 v dd k23 v dd m06 v dd m10 v dd m13 v dd m21 v dd n04 v dd n12 v dd n15 signals listed alphabetically (part 23 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor amcc 41 revision 1.01 ? november 1, 2004 data sheet v dd n19 power 57 v dd r02 v dd r10 v dd r13 v dd u08 v dd u23 v dd w06 v dd w13 v dd w21 v dd aa04 v dd aa12 v dd aa19 v dd ac10 v dd ac17 we y05 ddr sdram 51 signals listed alphabetically (part 24 of 24) signal name ball interface group page
440gx ? power pc 440gx embedded processor 42 amcc revision 1.01 ? november 1, 2004 data sheet in the following table, only the primary (default) signal name is shown for each pin. multiplexed or multifunction signals are marked with an asterisk (*). to determine what signals or functions are multiplexed on those pins, look up the primary signal name in signals listed alphabetically on page 18. signals listed by ball assignment (part 1 of 6) ball signal name ball signal name ball signal name ball signal name a01 no ball b01 no ball c01 no ball d01 pcixad36 a02 no ball b02 no ball c02 pcixad41 d02 ov dd a03 no ball b03 pcixad46 c03 pcixc5 * d03 pcixad45 a04 pcixad51 b04 ov dd c04 pcixad50 d04 gnd a05 drvrinh2 b05 pcixad54 c05 emctxerr * d05 pcixad53 a06 pcixad58 b06 gnd c06 pcixad57 d06 v dd a07 emcrxd2 * b07 pcixad62 c07 perblast d07 pcixad61 a08 pcixad42 b08 v dd c08 pcixc4 * d08 gnd a09 uartserclk b09 pcixad01 c09 pcixad55 d09 pcixack64 a10 pcixad05 b10 gnd c10 pcixad04 d10 ov dd a11 pcixframe b11 peraddr02 c11 peraddr01 d11 peraddr00 a12 peraddr03 b12 ov dd c12 pcixtrdy d12 gnd a13 peraddr12 b13 gnd c13 uart0_cts d13 v dd a14 pcixm66en b14 peraddr13 c14 peraddr14 d14 peraddr15 a15 pcixad09 b15 v dd c15 pcixad10 d15 gnd a16 peraddr11 b16 pcixad13 c16 pcixad14 d16 pcixad15 a17 pcixperr b17 gnd c17 pcixad00 d17 ov dd a18 pcixserr b18 uart0_dtr c18 uart1_rx * d18 peraddr05 a19 peraddr04 b19 ov dd c19 pcixc2 * d19 gnd a20 pcixad21 b20 peraddr16 c20 peraddr10 d20 pcixad20 a21 pcixad22 b21 gnd c21 pcixad23 d21 v dd a22 no ball b22 pcixad25 c22 pcixgnt1 * d22 pcixad30 a23 no ball b23 no ball c23 pcixad28 d23 gnd a24 no ball b24 no ball c24 no ball d24 pcixad31
440gx ? power pc 440gx embedded processor amcc 43 revision 1.01 ? november 1, 2004 data sheet e01 emcrxd1 * f01 pcixad35 g01 apv dd for pci pll h01 pcixad33 e02 pcixad40 f02 gnd g02 pcixad39 h02 v dd e03 pcixclk f03 pcixad44 g03 emcrxd0 * h03 pcixad32 e04 pcixad49 f04 v dd g04 pcixad48 h04 gnd e05 uart1_rts/dtr * f05 pcixad52 g05 pcixad43 h05 pcixad38 e06 pcixad56 f06 gnd g06 uart1_dsr/cts *h06 ov dd e07 pcixad60 f07 pcixad59 g07 pcixidsel h07 pcixad47 e08 pcixad63 f08 ov dd g08 pcix133cap h08 gnd e09 pcixreq64 f09 pcixc7 * g09 pcixc6 * h09 emcrxd3 * e10 pcixad03 f10 gnd g10 pcixad02 h10 ov dd e11 peraddr06 f11 pcixad06 g11 iic0sclk h11 iic1sclk * e12 pcixirdy f12 v dd g12 pcixad07 h12 gnd e13 pcixdevsel f13 gnd g13 iic0sda h13 ov dd e14 peradd09 f14 pcixc0 * g14 pcixad08 h14 iic1sda * e15 pcixad11 f15 ov dd g15 pcixad12 h15 gnd e16 pcixc1 * f16 pcixparlow g16 uart0_rts h16 uart0_ri e17 percs0 f17 gnd g17 uart0_rx h17 v dd e18 pcixad16 f18 pcixad18 g18 pcixad19 h18 perdata05 e19 pcixad17 f19 v dd g19 perdata04 h19 gnd e20 pcixreq2 f20 pcixc3 * g20 perdata03 h20 perdata02 e21 pcixreq1 * f21 gnd g21 pcixad26 h21 ov dd e22 pcixgnt0 f22 pcixad24 g22 sysclk h22 perdata01 e23 pcixad27 f23 ov dd g23 pcixreq4 h23 gnd e24 pcixreq0 f24 pcixad29 g24 asv dd for sysclk pll h24 perdata00 signals listed by ball assignment (part 2 of 6) ball signal name ball signal name ball signal name ball signal name
440gx ? power pc 440gx embedded processor 44 amcc revision 1.01 ? november 1, 2004 data sheet j01 agnd k01 emcrxdv * l01 gmcrefclk m01 peraddr21 j02 emcrxclk * k02 gnd l02 refven m02 ov dd j03 emctxd3 * k03 emcrxerr * l03 percs4 m03 peraddr07 j04 emctxd2 * k04 ov dd l04 pcixparhigh m04 gnd j05 pcixad37 k05 emctxd1 * l05 emcmdio m05 testen j06 emctxclk * k06 gnd l06 emctxen * m06 v dd j07 emccd * k07 emccrs * l07 gmctxer * m07 pcixint j08 emcmdclk k08 ov dd l08 pcixad34 m08 gnd j09 perdata19 k09 perdata28 l09 emctxd0 * m09 peroe j10 perdata18 k10 gnd l10 percs1 m10 v dd j11 perdata17 k11 perdata27 l11 uart0_tx m11 dmareq1 j12 perdata16 k12 v dd l12 pcixstop m12 gnd j13 perdata15 k13 gnd l13 percs6 m13 v dd j14 perdata14 k14 perdata26 l14 perdata20 m14 irq06 * j15 perdata13 k15 v dd l15 peraddr17 m15 gnd j16 uart1_tx * k16 perdata25 l16 perdata31 m16 eot3/tc3 * j17 perdata12 k17 gnd l17 perdata30 m17 ov dd j18 perdata11 k18 perdata24 l18 irq03 * m18 pcixgnt3 j19 perdata10 k19 ov dd l19 perdata29 m19 gnd j20 perdata9 k20 perdata23 l20 irq01 * m20 irq05 * j21 perdata8 k21 gnd l21 peraddr18 m21 v dd j22 perdata7 k22 perdata22 l22 peraddr19 m22 peraddr20 j23 perdata6 k23 v dd l23 pcixcap m23 gnd j24 agnd k24 perdata21 l24 peraddr22 m24 pcixreset signals listed by ball assignment (part 3 of 6) ball signal name ball signal name ball signal name ball signal name
440gx ? power pc 440gx embedded processor amcc 45 revision 1.01 ? november 1, 2004 data sheet n01 peraddr08 p01 dmareq3 * r01 trcts6 * t01 dqs7 n02 gnd p02 perwe r02 v dd t02 syserr n03 peraddr28 p03 trcts1 * r03 dmareq0 t03 percs5 n04 v dd p04 gmcrxer * r04 gnd t04 trcts0 * n05 dmaack0 p05 perr/w r05 trcclk t05 trces4 * n06 gnd p06 dmaack2 * r06 ov dd t06 trcts5 * n07 perready * p07 dmaack1 r07 trcts2 * t07 memdata61 n08 ov dd p08 trces3 * r08 gnd t08 memdata56 n09 trces2 * p09 trcts3 * r09 trcts4 * t09 memvref2 n10 gnd p10 sysreset r10 v dd t10 memdata38 n11 dmareq2 * p11 dmaack3 * r11 memdata42 t11 memdata37 n12 v dd p12 memdata28 r12 gnd t12 memdata35 n13 gnd p13 dm3 r13 v dd t13 memdata22 n14 irq04 * p14 gpio11 * r14 memdata14 t14 memvref1 n15 v dd p15 eot1/tc1 r15 gnd t15 memdata18 n16 trcbs0 * p16 eot2/tc2 * r16 eot0/tc0 t16 dm0 n17 gnd p17 trcbs1 * r17 ov dd t17 extreset n18 irq00 * p18 irq07 * r18 pcixreq5 t18 perwbe0 n19 v dd p19 pcixgnt5 r19 gnd t19 peraddr24 n20 irq08 * p20 irq02 * r20 pcixreq3 t20 trcbs2 * n21 gnd p21 trcts6 * r21 ov dd t21 trces0 * n22 pcixgnt2 p22 irq09 * r22 pcixgnt4 t22 perpar1 n23 ov dd p23 trces1 * r23 gnd t23 perpar0 n24 trst p24 peraddr23 r24 peraddr25 t24 percs3 signals listed by ball assignment (part 4 of 6) ball signal name ball signal name ball signal name ball signal name
440gx ? power pc 440gx embedded processor 46 amcc revision 1.01 ? november 1, 2004 data sheet u01 tmrclk v01 memdata55 w01 memdata58 y01 memdata51 u02 gnd v02 uart0_dsr w02 ov dd y02 memdata53 u03 percs7 v03 dm7 w03 memdata59 y03 dm6 u04 ov dd v04 percs2 w04 gnd y04 dqs6 u05 memdata63 v05 halt w05 memdata62 y05 we u06 gnd v06 memdata60 w06 v dd y06 memdata46 u07 memdata57 v07 memdata54 w07 ecc3 y07 memdata43 u08 v dd v08 memclkout0 w08 gnd y08 memdata47 u09 ecc4 v09 memclkout0 w09 clken3 y09 clken2 u10 gnd v10 memaddr12 w10 sv dd y10 memdata34 u11 memdata36 v11 memaddr9 w11 memdata32 y11 memaddr11 u12 sv dd v12 memdata31 w12 gnd y12 memdata30 u13 gnd v13 memaddr8 w13 v dd y13 memdata27 u14 memdata21 v14 memdata26 w14 banksel1 y14 memaddr7 u15 sv dd v15 memdata19 w15 gnd y15 memdata23 u16 memdata04 v16 memdata09 w16 memaddr10 y16 memdata20 u17 gnd v17 memdata05 w17 sv dd y17 memdata10 u18 perclk v18 irq10 * w18 memdata08 y18 memdata13 u19 ov dd v19 perwbe1 w19 gnd y19 memaddr00 u20 perpar3 v20 peraddr29 w20 perpar2 y20 memaddr02 u21 gnd v21 peraddr31 w21 v dd y21 holdack * u22 peraddr26 v22 tck w22 perwbe2 y22 tdo u23 v dd v23 peraddr30 w23 gnd y23 holdreq * u24 peraddr27 v24 uart0_dcd w24 perwbe3 y24 tdi signals listed by ball assignment (part 5 of 6) ball signal name ball signal name ball signal name ball signal name
440gx ? power pc 440gx embedded processor amcc 47 revision 1.01 ? november 1, 2004 data sheet aa01 memdata48 ab01 no ball ac01 no ball ad01 no ball aa02 gnd ab02 memdata50 ac02 no ball ad02 no ball aa03 memdata49 ab03 memdata52 ac03 ecc5 ad03 no ball aa04 v dd ab04 ecc6 ac04 gnd ad04 ecc7 aa05 dqs8 ab05 cas ac05 dm8 ad05 banksel3 aa06 gnd ab06 ecc1 ac06 sv dd ad06 ecc2 aa07 dm5 ab07 ecc0 ac07 memdata44 ad07 ras aa08 sv dd ab08 memdata40 ac08 gnd ad08 memdata41 aa09 dm4 ab09 memdata45 ac09 dqs5 ad09 ba1 aa10 gnd ab10 clken1 ac10 v dd ad10 memdata39 aa11 agnd ab11 amv dd for memclk pll ac11 dqs4 ad11 banksel2 aa12 v dd ab12 memdata29 ac12 gnd ad12 memdata33 aa13 gnd ab13 dqs3 ac13 sv dd ad13 memdata24 aa14 memdata16 ab14 dm2 ac14 dqs2 ad14 memdata25 aa15 sv dd ab15 banksel0 ac15 gnd ad15 memdata17 aa16 ba0 ab16 memdata11 ac16 dqs1 ad16 memaddr5 aa17 gnd ab17 memdata15 ac17 v dd ad17 clken0 aa18 dm1 ab18 memaddr6 ac18 memdata12 ad18 memaddr4 aa19 v dd ab19 memdata07 ac19 gnd ad19 memdata06 aa20 memdata03 ab20 memaddr3 ac20 dqs0 ad20 memaddr01 aa21 gnd ab21 memdata01 ac21 sv dd ad21 memdata00 aa22 extack * ab22 tms ac22 memdata02 ad22 no ball aa23 ov dd ab23 extreq * ac23 no ball ad23 no ball aa24 busreq * ab24 no ball ac24 no ball ad24 no ball signals listed by ball assignment (part 6 of 6) ball signal name ball signal name ball signal name ball signal name
440gx ? power pc 440gx embedded processor 48 amcc revision 1.01 ? november 1, 2004 data sheet signal description the ppc440gx embedded controller is provided in a 552-ball, ball grid array package. the following tables describe the package level pinout. in the table signal functional description on page 50, each i/o signal is listed along with a short description of its function. active-low signals (for example, ras ) are marked with an overline. please see signals listed alphabetically on page 18 for the pin (ball) number to which each signal is assigned. multiplexed signals some signals are multiplexed on the same pin so that the pin can be used for different functions. in most cases, the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same pin. if you need to know what, if any, signals are multiplexed with a particular signal, look up the name in signals listed alphabetically on page 18. it is expected that in any single app lication a particular pin will always be programmed to serve the same function. the flexibility of multiplexing allows a single chip to offer a richer pin selection than would otherwise be possible. multipurpose signals in addition to multiplexing, some pins are also multi- purpose. for example, the ebc peripheral controller address pins (peraddr00:31) are used as outputs by the ppc440g x to broadcast an address to external slave devices when the ppc440gx has control of the external bus. when du ring the course of normal chip operation an external master gains ownership of the external bus, these same pi ns are used as inputs which are driven by the external master and received by the ebc in the ppc440gx. in this example, the pins are also bidirectional, serving both as inputs and outputs. multimode signals in some cases (for example, ethernet) the function of a pin may vary with different modes of operation. when a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown. pin summary group no. of pins signal pins, non-multiplexed 343 signal pins, multiplexed 63 total signal pins 406 axv dd 3 agnd 3 ov dd 27 sv dd 9 v dd 34 gnd 70 total power pins 146 reserved 0 total pins 552
440gx ? power pc 440gx embedded processor amcc 49 revision 1.01 ? november 1, 2004 data sheet strapping pins one group of pins is used as strapped inputs during system reset. these pins function as strapped inputs only during reset and are used for other functions during normal operation (see strapping on page 83). note that these are not multiplexed pins since the function of the pins is not programmable.
440gx ? power pc 440gx embedded processor 50 amcc revision 1.01 ? november 1, 2004 data sheet signal functional description (part 1 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes pci-x interface pcixad00:63 address/data bus (bidirectional). i/o 3.3v pci pcixc0:7[be0:7 ] pci-x command[byte enables] . i/o 3.3v pci pcixcap capable of pci-x operation. i 3.3v lvttl 5 pcix133cap pci-x devices are 133 mhz capable. o 3.3v pci pcixclk provides timing to the pci in terface for pci transactions. note: if the pci-x interface is not bei ng used, drive this pin with a 3.3v clock signal at a frequency between 1 and 66mhz i 3.3v pci pcixdevsel indicates the driving device has decoded its address as the target of the current access. i/o 3.3v pci 4 pcixframe driven by the current master to indicate beginning and duration of an access. i/o 3.3v pci 4 pcixgnt0 indicates that the specified agent is granted access to the bus. when using an external pci/pci-x arbiter, connect the external arbiter's grant line to this signal. i/o 3.3v pci 4 pcixgnt1 indicates that the specified agent is granted access to the bus. i/o 3.3v pci 4 pcixgnt2:5 indicates that the specified agent is granted access to the bus. o 3.3v pci pcixidsel used as a chip select duri ng configuration read and write transactions. i 3.3v pci 5 pcixint level sensitive pci interrupt. o 3.3v pci pcixirdy indicates initiating agents ability to complete the current data phase of the transaction. i/o 3.3v pci 4 pcixm66en capable of 66mhz operation. i 3.3v lvttl w/pull-up 5 pcixparhigh even parity across pciad3 2:63 and pcixc0:3[be4:7]. i/o 3.3v pci pcixparlow even parity across pciad0 :31 and pcixc0:3[be0:3]. i/o 3.3v pci pcixperr reports data parity errors during all pci transactions except a special cycle. i/o 3.3v pci 4 pcixreq0 an indication to the pci-x arbiter that the specified agent wishes to use the bus. when using an exte rnal pci/pci-x arbiter, connect the external arbiter's re quest line to this signal. i/o 3.3v pci 4 pcixreq1:5 an indication to the pci-x arbiter that the specified agent wishes to use the bus. i 3.3v pci 4 pcixreq64 asserted by the current bus master, i ndicating a 64-bit transfer. i/o 3.3v pci 4 pcixack64 indicates the target can transfe r data using 64 bits. i/o 3.3v pci 4 pcixreset brings pci device regist ers and logic to a consistent state. o 3.3v pci pcixserr reports address parity errors, data parity errors on the special cycle command, or other ca tastrophic system errors. i/o 3.3v pci 4 pcixstop indicates the current target is requesting the master to stop the current transaction. i/o 3.3v pci 4
440gx ? power pc 440gx embedded processor amcc 51 revision 1.01 ? november 1, 2004 data sheet pcixtrdy i ndicates the target agents ability to complete the current data phase of the transaction. i/o 3.3v pci 4 ddr sdram interface ba0:1 bank address supporting up to four internal banks. o 2.5v sstl_2 banksel0:3 selects up to four external ddr sdram banks. o 2.5v sstl_2 cas column address strobe. o 2.5v sstl_2 clken0:3 clock enable. one for each bank. o 2.5v sstl_2 dm0:8 memory write data byte lane masks. memdm8 is the byte lane mask for the ecc byte lane. o 2.5v sstl_2 dqs0:8 byte lane data strobe. dqs8 is the data strobe for the ecc byte lane. i/o 2.5v sstl_2 ecc0:7 ecc check bits 0:7. i/o 2.5v sstl_2 memaddr00:12 memory address bus. o 2.5v sstl_2 memclkout0 memclkout0 subsystem clock. o 2.5v sstl_2 memdata00:63 memory data bus. i/o 2.5v sstl_2 memvref1:2 memory reference voltage (sv ref ) input. i voltage ref receiver ras row address strobe. o 2.5v sstl_2 we write enable. o 2.5v sstl_2 ethernet interface emccd, emc1rxerr, gmcgtxclk, gmc0txclk, tbitxclk, rtbi0txclk mii: collision detection rmii 1: receive error gmii: 1000mbps transmit clock rgmii: transmit clock tbi: transmit clock rtbi: transmit clock i/o 3.3v tolerant 2.5v cmos emccrs, emc0crsdv, gmctxd7, gmc1txd3, tbitxd7, rtbi1txd3 mii: carrier sense rmii 0: carrier sense data valid gmii: transmit data rgmii 1: transmit data tbi: transmit data rtbi 1: transmit data i/o 3.3v tolerant 2.5v cmos emcmdclk mii and rmii: management data clock o 3.3v tolerant 2.5v cmos emcmdio mii and rmii: transfer command and status information between mii and phy i/o 3.3v tolerant 2.5v cmos signal functional description (part 2 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
440gx ? power pc 440gx embedded processor 52 amcc revision 1.01 ? november 1, 2004 data sheet emcrxd0:3, emc0rxd0:1, emc1rxd0:1, emc0rxd, emc1rxd, emc2rxd, emc3rxd, gmctxd0:1, gmc0txd0:1, tbitxd0:1, rtbi0txd0:1 mii: receive data rmii 0: receive data rmii 1: receive data smii 0: receive data smii 1: receive data smii 2: receive data smii 3: receive data gmii: transmit data rgmii 0: transmit data tbi: transmit data rtbi 0: transmit data i/o 3.3v tolerant 2.5v cmos emcrxdv, emc1crsdv, gmctxd4, gmc1txd0, tbitxd4, rtbi1txd0 mii: receive data valid rmii 1: carrier sense data valid gmii: transmit data rgmii 1: transmit data tbi: transmit data rtbi 1: transmit data i/o 3.3v tolerant 2.5v cmos emcrxclk, gmctxd5, gmc1txd1, tbitxd5, rtbi1txd1 mii: receive clock gmii: transmit data rgmii 1: transmit data tbi: transmit data rtbi 1: transmit data i/o 3.3v tolerant 2.5v cmos emcrxerr, emc0rxerr, gmctxd6, gmc1txd2, tbitxd6, rtbi1txd2 mii: receive error rmii 0: receive error gmii: transmit data rgmii 1: transmit data tbi: transmit data rtbi 1: transmit data i/o 3.3v tolerant 2.5v cmos emctxclk, emcrefclk mii: transmit clock rmii and smii: reference clock i 3.3v tolerant 2.5v cmos 5 emctxd0:3, emc0txd0:1, emc1txd0:1, emc0txd, emc1txd, emc2txd, emc3txd, gmctxd2:3, gmc0txd2:3, tbitxd2:3, rtbi0txd2:3 mii: transmit data rmii 0: transmit data rmii 1: transmit data smii 0: transmit data smii 1: transmit data smii 2: transmit data smii 3: transmit data gmii: transmit data rgmii 0: transmit data tbi: transmit data rtbi 0: transmit data o 3.3v tolerant 2.5v cmos emctxen, emc0txen, emcsync mii: transmit data enabled rmii 0: transmit data enabled smii: sync signal o 3.3v tolerant 2.5v cmos emctxerr, emc1txen, gmcrxclk, gmc0rxclk, tbirxclk0, rtbi0rxclk mii: transmit error: rmii: transmit data enabled gmii: receive clock rgmii: receive clock tbi: receive clock 0 rtbi: receive clock i/o 3.3v tolerant 2.5v cmos gmccd, gmc1rxclk, rtbi1rxclk gmii: collision detection rgmii: receive clock rtbi: receive clock i 3.3v tolerant 2.5v cmos 5 signal functional description (part 3 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
440gx ? power pc 440gx embedded processor amcc 53 revision 1.01 ? november 1, 2004 data sheet gmccrs, gmc1txclk, rtbi1txclk gmii: carrier sense rgmii: transmit clock rtbi: transmit clock i/o 3.3v tolerant 2.5v cmos gmcrefclk gmii, rgmii, tbi and rt bi: gigabit reference clock i 3.3v tolerant 2.5v cmos 5 gmcrxd0:3, gmc0rxd0:3, tbirxd0:3, rtbi0rxd0:3 gmii: receive data rgmii: receive data tbi: receive data rtbi: receive data i 3.3v tolerant 2.5v cmos gmcrxd4:7, gmc1rxd0:3, tbirxd4:7, rtbi1rxd0:3 gmii: receive data rgmii: receive data tbi: receive data rtbi: receive data i 3.3v tolerant 2.5v cmos gmcrxdv, gmc0rxctl, tbirxd8, rtbi0rxd4 gmii: receive data valid rgmii: receive control tbi: receive data rtbi: receive data i 3.3v tolerant 2.5v cmos gmcrxer, gmc1rxctl, tbirxd9, rtbi1rxd4 gmii: receive error rgmii: receive control tbi: receive data rtbi: receive data i 3.3v tolerant 2.5v cmos gmctxen, gmc0txctl, tbitxd8, rtbi0txd4 gmii: transmit data enable rgmii: transmit control tbi: transmit data rtbi: transmit data o 3.3v tolerant 2.5v cmos gmctxer, gmc1txctl, tbitxd9, rtbi1txd4 gmii: transmit error rgmii: transmit control tbi: transmit data rtbi: transmit data o 3.3v tolerant 2.5v cmos gmctxclk tbirxclk1 gmii: 10/100mbps transmit clock tbi: receive clock 1 i/o 3.3v lvttl 5 external slave peripheral interface dmaack0:3 used by the ppc440gx to indica te that data transfers have occurred. o 3.3v tolerant 2.5v cmos dmareq0:3 used by slave peripherals to indica te they are prepared to transfer data. i 3.3v tolerant 2.5v cmos 1, 5 eot0:3/tc0:3 end of transfer/terminal count. i/o 3.3v tolerant 2.5v cmos 1, 5 peraddr00:31 peripheral address bus used by ppc440gx when not in external master mode, otherwise used by external master. note: peraddr00 is the most significant bit (msb) on this bus. i/o 3.3v lvttl 1 perwbe0:3 external peripheral data bus byte enables. i/o 3.3v lvttl 1, 2 perblast used by either the peripheral c ontroller, dma controller, or external master to indicates the last transfer of a memory access. i/o 3.3v lvttl 1, 4 percs0:7 external peripheral devi ce select. o 3.3v lvttl 2 perdata00:31 peripheral data bus used by ppc440gx when not in external master mode, otherwise used by external master. note: perdata00 is the most significant bit (msb) on this bus. i/o 3.3v lvttl 1 signal functional description (part 4 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
440gx ? power pc 440gx embedded processor 54 amcc revision 1.01 ? november 1, 2004 data sheet peroe used by either peripheral contro ller or dma controller depending upon the type of transfer involved. when the ppc440gx is the bus master, it enables the sele cted ddr sdrams to drive the bus. o 3.3v lvttl 2 perpar0:3 external peripheral data bus byte parity. i/o 3.3v lvttl 1 perready used by a peripheral slave to indicate it is ready to transfer data. i 3.3v lvttl perr/w used by the ppc440gx when not in external master mode, as output by either the peripheral controller or dma controller depending upon the type of transfe r involved. high indicates a read from memory, low indicates a write to memory. otherwise, it used by the external master as an input to indicate the direction of transfer. i/o 3.3v lvttl 1, 2 perwe write enable. low when any of the four perwbe0:3 signals are low. o 3.3v lvttl 2 external master peripheral interface busreq bus request. used when the ppc440gx needs to regain control of peripheral interface from an external master. o 3.3v lvttl extack external acknowledgement. used by the ppc440gx to indicate that a data transfer occurred. o 3.3v lvttl extreq external request. used by an exter nal master to indicate it is prepared to transfer data. i 3.3v lvttl 1, 4 extreset peripheral reset. used by an external master and by synchronous peripheral slaves. o 3.3v lvttl holdack hold acknowledge. used by t he ppc440gx to transfer ownership of peripheral bus to an external master. o 3.3v lvttl holdreq hold request. used by an exter nal master to request ownership of the peripheral bus. i 3.3v lvttl 1, 5 perclk peripheral clock. used by an exte rnal master and by synchronous peripheral slaves. o 3.3v lvttl pererr external error. used as an input to record external master errors and external slave peripheral errors. i/o 3.3v lvttl 1, 5 uart peripheral interface uartserclk serial clock input that provides an alternative to the internally generated serial clock. used in cases where the allowable internally generated clock rates are not satisfactory. this input can be individually connect ed to either or both uart0 and uart1. i 3.3v lvttl 1, 4 uart0_rx uart0 receive data. i 3.3v lvttl 1, 4 uart0_tx uart0 transmit data. o 3.3v lvttl 4 uart0_dcd uart0 data carrier detect. i 3.3v lvttl 6 uart0_dsr uart0 data set ready. i 3.3v lvttl 6 uart0_cts uart0 clear to send. i 3.3v lvttl 1, 4 uart0_dtr uart0 data terminal ready. o 3.3v lvttl 4 uart0_rts uart0 request to send. o 3.3v lvttl 4 uart0_ri uart0 ring indicator. i 3.3v lvttl 1, 4 signal functional description (part 5 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
440gx ? power pc 440gx embedded processor amcc 55 revision 1.01 ? november 1, 2004 data sheet uart1_rx uart1 receive data. i/o 3.3v lvttl 1, 4 uart1_tx uart1 transmit data. i/o 3.3v lvttl 1, 4 uart1_dsr /cts uart1 data set ready or clear to send. the choice is determined by a dcr register bit setting. i/o 3.3v lvttl 1, 4 uart1_rts/dtr uart1 request to send or data terminal ready. the choice is determined by a dcr register bit setting. i/o 3.3v lvttl 1, 4 iic peripheral interface iic0sclk iic0 serial clock. i/o 3.3v lvttl 1, 2 iic0sda iic0 serial data. i/o 3.3v lvttl 1, 2 iic1sclk iic1 serial clock. i/o 3.3v iic 1, 2 iic1sda iic1 serial data. i/o 3.3v iic 1, 2 interrupts interface irq00:10 external interrupt reques ts 0 through 10. i 3.3v lvttl 1, 5 irq11:12 external interrupt requests 11 through 12. i 3.3v pci irq13:17 external interrupt requests 13 through 17. i 3.3v lvttl jtag interface tck test clock. i 3.3v lvttl w/pull-up 1 tdi test data in. i 3.3v lvttl w/pull-up 4 tdo test data out. o 3.3v lvttl tms test mode select. i 3.3v lvttl w/pull-up 1 trst test reset. during chip power-up, this signal must be low from the start of v dd ramp-up until at least 16 sysclk cycles after v dd is stable in order to initialize the jtag controller. i 3.3v lvttl w/pull-up 5 signal functional description (part 6 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
440gx ? power pc 440gx embedded processor 56 amcc revision 1.01 ? november 1, 2004 data sheet system interface sysclk main system clock input. clock 3.3v lvttl syserr set to 1 when a machine check is generated. o 3.3v lvttl sysreset main system reset. external logic can drive this bi directional pin low (minimum of 16 cycles) to initiate a system reset. a system reset can also be initiated by so ftware. the signal is implemented as an open-drain output (two states; 0 or open circuit). during chip power-up, this signal must be low from the start of v dd ramp-up until at least 16 sysclk cycles after v dd is stable. i/o 3.3v lvttl 1, 2 tmrclk processor timer external input clock. i 3.3v lvttl halt halt from external debugger. i 3.3v lvttl 1, 4 gpio00:31 general purpose i/o 0 through 10. to access these functions, software must set dcr register bits. i/o 3.3v lvttl testen test enable. i 3.3v tolerant 2.5v cmos 3 rcvrinh receiver inhibit. active only when testen is active. i 3.3v lvttl refven reference voltage enable. used for wafer testing. do not connect for normal operation. i 3.3v lvttl w/pull-down drvrinh2 driver inhibit. used for test pur poses only. tie up for normal operation i 3.3v lvttl w/pull-up 2 signal functional description (part 7 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
440gx ? power pc 440gx embedded processor amcc 57 revision 1.01 ? november 1, 2004 data sheet trace interface trcbs0:2 trace branch execut ion status. i/o 3.3v lvttl trcclk trace data capture cl ock, runs at 1/4 the frequency of the processor. o 3.3v lvttl trces0:4 trace execution status is presented every fourth processor clock cycle. i/o 3.3v lvttl trcts0:5 (multiplexed with gpio signals) additional information on trac e execution and branch status. note: the trace signals, trcts0:6, are duplicated on two sets of chip balls and are multiplexed with other signals in both cases. this allows user s to choose which set of multiplexed signals they wish to use along with the trcts0:6 signals. the trac e signals in this set are primary signals. i/o 3.3v tolerant 2.5v cmos trcts1:5 (multiplexed with ebc signals) additional information on trac e execution and branch status. note: the trace signals in this set are secondary signals. i/o 3.3v lvttl trcts6 (multiplexed with ebc and ethernet signals) additional information on trac e execution and branch status. note: this trace signal is the primary signal. i/o 3.3v lvttl power pins agnd pll (analog) voltage ground. n/a n/a gnd ground. n/a n/a axv dd 1.5vfiltered voltages input for plls (analog circuits) note: a separate filter for each of the three voltages is recommended. n/a n/a ov dd 3.3v supplyi/o (except ddr sdram, ethernet) n/a n/a sv dd 2.5v supplyddr sdram, ethernet n/a n/a v dd 1.5v supplylogic voltage. n/a n/a signal functional description (part 8 of 8) notes: 1. receiver input has hysteresis 2. must pull up (recommended value is 3k ? to 3.3v ) 3. must pull down (recommended value is 1k ? ) 4. if not used, must pull up (recommended value is 3k ? to 3.3v) 5. if not used, must pull down (recommended value is 1k ? ) 6. strapping input during rese t; pull-up or pull-down required signal name description i/o type notes
440gx ? power pc 440gx embedded processor 58 amcc revision 1.01 ? november 1, 2004 data sheet absolute maximum ratings the absolute maximum ratings bel ow are stress ratings only. operation at or beyond thes e maximum ratings can cause permanent damage to the device. none of the performance spec ification contained in this document are guaranteed when operating at these maximum ratings. characteristic symbol value unit notes supply voltage (internal logic) v dd 0 to +1.65 v supply voltage (i/o interface, except ddr sdram) ov dd 0 to +3.6 v pll supply voltages axv dd 0 to +1.65 v 1 supply voltage (ddr sdram logic) sv dd 0 to +2.7 v input voltage (3.3v lvttl receivers) v in 0 to +3.6 v storage temperature range t stg -55 to +150 c case temperature under bias t c -40 to +120 c2 notes: 1. the analog voltages used for the on-chip p lls can be derived from the logic voltage, but must be filtered before entering the ppc440gx. a separate filter, as shown below, is recommended for each voltage: 2. this value is not a specificatio n of the operational temperature ran ge, it is a stress rating only. v dd c axv dd l l C smt ferrite bead chip, murata blm31a700s c C 0.1 f ceramic
440gx ? power pc 440gx embedded processor amcc 59 revision 1.01 ? november 1, 2004 data sheet package thermal specifications thermal resistance values for the cbga and pbga pa ckages in a convection environment are as follows: parameter symbol package airflow ft/min (m/sec) unit notes 0 (0) 100 (0.51) 200 (1.02) junction-to-case thermal resistance jc ceramic <0.1 <0.1 <0.1 c/w 1 plastic 1.2 1.2 1.2 c/w 1, 3 case-to-ambient thermal resistance (w/o heat sink) ca ceramic 18.9 17.7 16.3 c/w 2 plastic 20.8 c/w 2, 3 range min nom max junction-to-ball (typical) jb ceramic 1.5 2.2 c/w 4 plastic c/w notes: 1. case temperature, t c , is measured at top center of case su rface with device soldered to circuit board. 2. the case-to-ambient thermal resistance is measured in a jedec jesd51-6 standard env ironment; and may not accurately predict thermal performance in production equip ment environments. the operational ca se temperature must be maintained. 3. modeled on standard jedec 2s2p card, 50x50mm 4. 1.5 c/w is the theoretical jb using an infinite heat sink. the larger number applie s to the module mounted on a 1.8mm thick, 2p card using 1oz. copper power planes, with an effective heat transfer area of 75mm 2 .
440gx ? power pc 440gx embedded processor 60 amcc revision 1.01 ? november 1, 2004 data sheet heat sink mounting inform ation (ceramic package only) proper thermal design is primarily dependent upon multiple system-level effects; that is, the effects of the heat sink, the air flow, and the thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, sp ring clips to the printed-circuit board or package, or a mounting clip and screw assembly. when attaching heat sinks, it is important to avoid placing excessive mechanical stress on bonding of the chip to the substrate and the package to the board. heat sink attached with spring clip heat sink attached with adhesive important: all of the guidelines indicated in the above diagrams must be evaluated and adjusted to account for the shock and vibration effects of any particular application. heat sink thermal grease printed circuit board cbga package heat sink heat sink clip printed circuit board cbga package spring clip to board spring clip to package thermal grease heat sink clip heat sink clip heat sink clip static compression (spring force)2.27kg maximum static compression (spring force)2.27kg maximum 1 note 1: force is limited by allowable compression on the die. allowable package compression force is 4.4kg. heat sink printed circuit board cbga package adhesive heat sink printed circuit board cbga package adhesive heat sink weight force60g maximum weight force weight force
440gx ? power pc 440gx embedded processor amcc 61 revision 1.01 ? november 1, 2004 data sheet recommended dc oper ating conditions device operation beyond the conditions specified is no t recommended. extended operation beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes logic supply voltage (500mhz rev a and 533mhz) v dd +1.4 +1.5 +1.6 v 4 logic supply voltage (667mhz and 800mhz) v dd +1.5 +1.55 +1.6 v 4 i/o supply voltage ov dd +3.0 +3.3 +3.6 v 4 ddr sdram supply voltage sv dd +2.3 +2.5 +2.7 v 4 pll supply voltages (500mhz rev a and 533mhz) axv dd +1.4 +1.5 +1.6 v 3 pll supply voltage (667mhz and 800mhz) axv dd +1.5 +1.55 +1.6 v 3 ddr sdram reference voltage sv ref +1.15 +1.25 +1.35 v 3 input logic high (2.5v sstl) v ih sv ref +0.18 sv dd +0.3 v2 input logic high (2.5v cmos, 3.3v tolerant receiver) 1.7 v input logic high (3.3v pci-x) 0.5ov dd ov dd +0.5 v1 input logic high (3.3v lvttl) +2.0 +3.6 v input logic low (2.5v sstl) v il -0.3 sv ref -0.18 v input logic low (2.5v cmos, 3.3v tolerant receiver) 0.7 v input logic low (3.3v pci-x) -0.5 0.35ov dd v1 input logic low (3.3v lvttl) 0 +0.8 v output logic high (2.5v sstl) v oh +1.95 sv dd v output logic high (2.5v cmos, 3.3v tolerant receiver) 2.0 v output logic high (3.3v pci-x) 0.9ov dd ov dd v1 output logic high (3.3v lvttl) +2.4 ov dd v output logic low (2.5v sstl) v ol 00.55v output logic low (2.5v cmos, 3.3v tolerant receiver) 0.4 v output logic low (3.3v pci-x) 0.1ov dd v1 output logic low (3.3v lvttl) 0 +0.4 v input leakage current (no pull-up or pull-down) i il1 00 a input leakage current for pull-down i il2 0 (lpdl) 200 (mpul) a 5 input leakage current for pull-up i il3 -150 (lpdl) 0 (mpul) a 5 input max allowable overshoot (3.3v lvttl) v imao +3.9 v input max allowable undershoot (3.3v lvttl) v imau -0.6 v output max allowable overshoot (3.3v lvttl) v omao +3.9 v
440gx ? power pc 440gx embedded processor 62 amcc revision 1.01 ? november 1, 2004 data sheet output max allowable undershoot (3.3v lvttl) v omau3 -0.6 v case temperature rating c t c -40 +85 c6 case temperature rating e (533mhz ceramic only) t c -40 +105 c6 notes: 1. pci-x drivers meet pci-x specifications. 2. sv ref = sv dd /2 3. the analog voltages used for the on-chip plls can be derived from the logic voltage, but must be filtered before entering the ppc440gx. see absolute maximum ratings on page 58. 4. during chip power-up, ov dd should begin to ramp before v dd . external voltage should not be applied to the chip i/o pins before ov dd is applied to the chip. a power -down cycle should complete (ov dd and v dd should both be below 0.4v) before a new power- up cycle is started. 5. lpdl is least positive down level; mpul is most positive up level. 6. case temperature, t c , is measured at top center of case su rface with device sol dered to circuit board. input capacitance parameter symbol maximum unit notes group 1 (2.5v sstl i/o) c in1 12 pf group 2 (3.3v lvttl i/o) c in2 12 pf group 3 (pci-x i/o) c in3 12 pf group 4 (receivers) c in4 9pf group 5 (3.3v tolerant cmos i/o) c in5 16 pf recommended dc oper ating conditions (continued) device operation beyond the conditions specified is no t recommended. extended operation beyond the recommended conditions can affect device reliability. parameter symbol minimum typical maximum unit notes
440gx ? power pc 440gx embedded processor amcc 63 revision 1.01 ? november 1, 2004 data sheet test conditions clock timing and switching characteristics ar e specified in accordance with operating conditions shown in the table recommended dc operating conditions. ac specifications are characterized with v dd = 1.5v, t c = +85 c and a 10pf test load as shown in the figure to the right. dc power supply loads parameter symbol frequency (mhz) typical maximum unit notes v dd active operating current i dd 533 1.37 1.69 a 2 667 1.49 1.8 a 2 800 1.77 2.2 a 2, 3 ov dd active operating current i odd 533 58 111 ma 2 667 58 111 ma 2 800 58 111 ma 2, 3 sv dd active operating current i sdd 533 544 940 ma 2 667 568 837 ma 2 800 680 749 ma 2, 3 axv dd input current i add 33 ma 1, 2 notes: 1. see absolute maximum ratings on page 58 for filter recommendations. 2. the maximum current values listed above are not guaranteed to be the highest obtainable. these values are dependent on many factors including the type of applications running, cl ock rates, use of internal functional c apabilities, external interface usage, cas e temperature, and the power supply voltages. your specific application can produce si gnificantly different results. v dd (logic) current and power are primarily dependent on the appl ications running and the use of internal chip functions (dma, pci, ethernet, and so on). ov dd (i/o) current and power are primarily dependent on th e capacitive loading, frequency, and utilizat ion of the external buses. the foll owing information provides details about the conditions under which th e listed values were obtained: a. in general, the values are measured us ing a ppc440gx evaluation board set for ether net mode 4, pci-x running at 100mhz with an intel pro 1000, an agilent test card, an ebmi test card , a uart wrap plug, and one 128mb micron dimm while running applications designed to maximize cpu power consumption. an external pci master heavily loads the pci bus with transfers targeting sdram, while the internal dma cont roller further increases sdram bus traffic. system clock rates are set as follows: sysclk = 33mh z, cpu = 667mhz, plb = 167mhz, and opb = ebc = 83mhz. b. typical current is characterized at v dd = +1.5v, ov dd = +3.3v, sv dd = +2.5v, and t c = +47 c. c. maximum current is characterized at v dd = +1.6v, ov dd = +3.6v, sv dd = +2.7v, and t c = +85 c. 3. estimated values. output pin 10pf c
440gx ? power pc 440gx embedded processor 64 amcc revision 1.01 ? november 1, 2004 data sheet timing waveform clocking specifications symbol parameter min max units sysclk input f c frequency 33.33 83.33 mhz t c period 12 30 ns t cs edge stability C 0.15 ns t ch high time 40% of nominal period 60% of nominal period ns t cl low time 40% of nominal period 60% of nominal period ns note: input slew rate 1v/ns pll vco f c frequency 600 1334 mhz t c period 0.75 1.66 ns processor clock f c frequency 300 800 mhz t c period 1.25 C ns memclkout f c frequency 100 166.66 mhz t c period 6 10 ns t ch high time 45% of nominal period 55% of nominal period ns opb clock f c frequency 33.33 83.33 mhz t c period 12 30 ns t cl t ch t c 2.0v 1.5v 0.8v
440gx ? power pc 440gx embedded processor amcc 65 revision 1.01 ? november 1, 2004 data sheet spread spectrum clocking care must be taken when using a spread spectrum clock generator (sscg) with the ppc440gx. this controller uses a pll for clock generation inside the chip. the accuracy with which the pll follows the sscg is referred to as tracking skew. the pll bandwidth and phase angle determine how much tracking skew there is between the sscg and the pll for a given frequency deviation and modulation frequency. when using an sscg with the ppc440gx the following conditions must be met: ? the frequency deviation must not violate the minimu m clock cycle time. therefore, when operating the ppc440gx with one or more in ternal clocks at their ma ximum supported fr equency, the sscg can only lower the frequency. ? the maximum frequency de viation cannot exceed ? 3%, and the modulation frequency cannot exceed 40khz. in some cases, on-board ppc440gx peripherals impose more stringent requirements. ? use the peripheral bus clock for logic that is synchronous to the peripheral bus since this clock tracks the modulation. ? use the ddr sdram memclkout sinc e it also tracks the modulation. ? for pci-x and pci 66 the maximum spread spectrum is -1% modulated between 30khz and 33khz. notes: 1. the serial port baud rates are synchronous to the modulated clock. the serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. the 1.5% tolerance assumes that the connected device is running at precise baud rates. 2. ethernet operation is unaffected. 3. iic operation is unaffected. important: it is up to the system designer to ensure that any sscg used with the ppc440gx meets the above requirements and does not adversely affect other aspects of the system.
440gx ? power pc 440gx embedded processor 66 amcc revision 1.01 ? november 1, 2004 data sheet peripheral interface clock timings parameter min max units notes pcixclk input frequency (asynchronous mode) C 133.33 mhz 2 pcixclk period (asynchronous mode) 7.5 C ns pcixclk input high time 40% of nominal period 60% of nominal period ns pcixclk input low time 40% of nominal period 60% of nominal period ns emcmdclk output frequency C 2.5 mhz emcmdclk period 400 C ns emcmdclk output high time 160 C ns emcmdclk output low time 160 C ns emctxclk input frequency mii(rmii) 2.5(5) 25(50) mhz emctxclk period mii(rmii) 40(20) 400(200) ns emctxclk input high time 35% of nominal period C ns emctxclk input low time 35% of nominal period C ns emcrxclk input frequency mii(rmii) 2.5(5) 25(50) mhz emcrxclk period mii(rmii) 40(20) 400(200) ns emcrxclk input high time 35% of nominal period C ns emcrxclk input low time 35% of nominal period C ns gmcrefclk input frequency C 125 mhz
440gx ? power pc 440gx embedded processor amcc 67 revision 1.01 ? november 1, 2004 data sheet gmcrefclk period 8 ns gmcrefclk input high time 47% of nomi nal period 53% of nominal period ns gmcrefclk input low time 47% of nomi nal period 53% of nominal period ns perclk output frequency (for ext. mast er or sync. slaves) 33.33 83.33 mhz perclk period 12 30 ns perclk output high time 50% of nominal period 66% of nominal period ns perclk output low time 33% of nominal period 50% of nominal period ns uartserclk input frequency C 1000/(2t opb 1 +2ns) mhz 1 uartserclk period 2t opb +2 Cns1 uartserclk input high time t opb +1 Cns1 uartserclk input low time t opb +1 Cns1 tmrclk input frequency C 100 mhz tmrclk period 10 C ns tmrclk input high time 40% of nominal period 60% of nominal period ns tmrclk input low time 40% of nominal period 60% of nominal period ns notes: 1. t opb is the period in ns of the opb clock. the internal opb cl ock runs at an integral divisor ratio of the frequency of the plb clock. the maximum opb cloc k frequency is 83.33 mhz. refer to the clocking chapter of the ppc440gx embedded processor user?s manual for details. 2. when the pci-x interface is used to support a legacy pci interface, the maximum pcixclk frequency is 66.66mhz. peripheral interface cl ock timings (continued) parameter min max units notes
440gx ? power pc 440gx embedded processor 68 amcc revision 1.01 ? november 1, 2004 data sheet input setup and hold waveform output delay and fl oat timing waveform clock t is t ih min min inputs valid valid clock outputs valid t oh min t ov max t ov max t oh min t ov max t oh min float (high-z) high (drive) low (drive)
440gx ? power pc 440gx embedded processor amcc 69 revision 1.01 ? november 1, 2004 data sheet i/o specificationsall speeds (part 1 of 4) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. pci-x timings are for asynchronous operation up to 133mhz. pc i-x input setup time requirement is 1.2ns for 133mhz and 1.7ns for 66mhz. pci timings (in parentheses) are for asyn chronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. 3. the clock frequency for rmii operation is 50mhz 100ppm. 4. the clock frequency for smii operation is 125mhz 100ppm. 5. these are ddr signals that can change on bo th the positive and negative clock transitions. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) pci-x interface pcixad00:63 note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixc3:0[be3:0 ] note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixparlow note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pciparhigh note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixframe note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixint n/a n/a dc dc 0.5 1.5 pcixclk async pcixirdy note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixtrdy note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixstop note 2 (3 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixdevsel note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixidsel note 2 (3) 0.5 (0) n/a n/a n/a n/a pcixclk 2 pcixperr note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixserr note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixclk dc dc n/a n/a n/a n/a async pcixreset n/a n/a n/a n/a n/a n/a pcixclk pcixreq64 note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixack64 note 2 (3) 0.5 (0) 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 pcixcap note 2 (3) 0.5 (0) n/a n/a n/a n/a pcixclk 2 pcix133cap 3.8 0.7 0.5 1.5 pcixclk 2 pcixm66en note 2 (3) 0.5 (0) n/a n/a n/a n/a pcixclk 2 pcixreq0:5 note 2 (3) 0.5 (0) n/a n/a n/a n/a pcixclk 2 pcixgnt0:5 n/a) n/a 3.8 (6) 0.7 (note 2) 0.5 1.5 pcixclk 2 ethernet mii interface emcrxd0:3 4 1 n/a n/a 5.1 6.8 emcrxclk 1 emcrxdv 4 1 n/a n/a 5.1 6.8 emcrxclk 1 emcrxclk n/a n/a n/a n/a 5.1 6.8 1, async emcrxerr 4 1 n/a n/a 5.1 6.8 emcrxclk 1 emctxd0:3 n/a n/a 15 2 5.1 6.8 emctxclk 1 emctxen n/a n/a 15 2 5.1 6.8 emctxclk 1 emctxclk n/a n/a n/a n/a n/a n/a 1, async emctxerr n/a n/a 15 2 5.1 6.8 emctxclk 1 emccrs n/a n/a 5.1 6.8 1, async emccd n/a n/a 5.1 6.8 1, async emcmdio 5.1 6.8 emcmdclk 1 emcmdclk n/a n/a n/a n/a 5.1 6.8 1, async
440gx ? power pc 440gx embedded processor 70 amcc revision 1.01 ? november 1, 2004 data sheet ethernet rmii interface emc0rxd0:1 2 1 n/a n/a 5.1 6.8 emcrefclk emc0rxerr 2 1 n/a n/a 5.1 6.8 emcrefclk emc0crsdv n/a n/a 5.1 6.8 emcrefclk emc0txd0:1 n/a n/a 11 2 5.1 6.8 emcrefclk emc0:1txen n/a n/a 11 2 5.1 6.8 emcrefclk emc1rxd0:1 n/a n/a 5.1 6.8 emcrefclk emc1rxerr n/a n/a 5.1 6.8 emcrefclk emc1crsdv n/a n/a 5.1 6.8 emcrefclk emc1txd0:1 n/a n/a 11 2 5.1 6.8 emcrefclk emcrefclk n/a n/a n/a n/a n/a n/a 3, async ethernet smii interface emc0:1rxd 0.8 0.8 n/a na/ 5.1 6.8 emcrefclk emc2:3rxd 0.8 0.8 n/a na/ 5.1 6.8 emcrefclk emc0:1txd n/a n/a 6.2 2 5.1 6.8 emcrefclk emc2:3txd n/a n/a 6.2 2 5.1 6.8 emcrefclk emcrefclk n/a n/a n/a n/a n/a n/a 4, async ethernet gmii interface gmcrxclk n/a n/a n/a n/a n/a n/a 1, async gmcrxd0:7 2 0 n/a n/a 5.1 6.8 gmcrxclk gmcrxer 2 0 n/a n/a 5.1 6.8 gmcrxclk gmcrxdv 2 0 n/a n/a 5.1 6.8 gmcrxclk gmccrs n/a n/a 5.1 6.8 1, async gmcol n/a n/a 5.1 6.8 1, async gmcgtxclk n/a n/a n/a n/a n/a n/a 1, async gmctxd0:7 n/a n/a 5.5 0.5 5.1 6.8 gmcgtxclk gmctxer n/a n/a 5.5 0.5 5.1 6.8 gmcgtxclk gmctxen n/a n/a 5.5 0.5 5.1 6.8 gmcgtxclk ethernet rgmii interface gmc0rxclk n/a n/a n/a n/a n/a n/a 1, async gmc0rxctl 1 1 n/a n/a n/a n/a gmc0rxclk 4, 5 gmc0rxd0:3 1 1 n/a n/a 5.1 6.8 gmc0rxclk 4, 5 gmc0txclk n/a n/a n/a n/a 5.1 6.8 1, async gmc0txctl n/a n/a 0.5 3.5 5.1 6.8 gmc0txclk 4, 5 gmc0txd0:3 n/a n/a 0.5 3.5 5.1 6.8 gmc0txclk 4, 5 gmc1rxclk n/a n/a n/a n/a n/a n/a 1, async gmc1rxctl 1 1 n/a n/a n/a n/a gmc1rxclk 4, 5 gmc1rxd0:3 1 1 n/a n/a 5.1 6.8 gmc1rxclk 4, 5 gmc1txclk n/a n/a n/a n/a 5.1 6.8 1, async gmc1txctl n/a n/a 0.5 3.5 5.1 6.8 gmc1txclk 4, 5 gmc1txd0:3 n/a n/a 0.5 3.5 5.1 6.8 gmc1txclk 4, 5 gmcrefclk n/a n/a n/a n/a n/a n/a async i/o specificationsall speeds (part 2 of 4) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. pci-x timings are for asynchronous operation up to 133mhz. pc i-x input setup time requirement is 1.2ns for 133mhz and 1.7ns for 66mhz. pci timings (in parentheses) are for asyn chronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. 3. the clock frequency for rmii operation is 50mhz 100ppm. 4. the clock frequency for smii operation is 125mhz 100ppm. 5. these are ddr signals that can change on bo th the positive and negative clock transitions. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum)
440gx ? power pc 440gx embedded processor amcc 71 revision 1.01 ? november 1, 2004 data sheet ethernet tbi interface tbirxclk0 n/a n/a n/a n/a n/a n/a 1, async tbirxclk1 n/a n/a n/a n/a n/a n/a 1, async tbirxd0:9 2.5 1.5 n/a n/a 5.1 6.8 tbirxclkx tbitxclk n/a n/a n/a n/a n/a n/a 1, async tbitxd0:9 n/a n/a 6 1 5.1 6.8 tbitxclk ethernet rtbi interface rtbi0rxclk n/a n/a n/a n/a n/a n/a 1, async rtbi0rxd0:4 1 1 n/a n/a 5.1 6.8 rtbi0rxclk rtbi0txclk n/a n/a n/a n/a 5.1 6.8 1, async rtbi0txd0:4 n/a n/a 3.5 5.1 5.1 6.8 rtbi0txclk rtbi1rxclk n/a n/a n/a n/a n/a n/a 1, async rtbi1rxd0:4 1 1 n/a n/a 5.1 6.8 rtbi1rxclk rtbi1txclk n/a n/a n/a n/a 5.1 6.8 1, async rtbi1txd0:4 n/a n/a 3.5 5.1 5.1 6.8 rtbi1txclk gmcrefclk n/a n/a n/a n/a n/a n/a async internal peripheral interface iic0sclk n/a n/a n/a n/a 15.3 10.2 iic0sda 15.3 10.2 iic1sclk n/a n/a n/a n/a 15.3 10.2 iic1sda 15.3 10.2 uartserclk n/a n/a n/a n/a n/a n/a uart0_rx n/a n/a n/a n/a uart0_tx n/a n/a 10.3 7.1 uart0_dcd n/a n/a n/a n/a uart0_dsr n/a n/a n/a n/a uart0_cts n/a n/a n/a n/a uart0_dtr n/a n/a 10.3 7.1 uart0_ri n/a n/a n/a n/a uart0_rts n/a n/a 10.3 7.1 uart1_rx n/a n/a n/a n/a uart1_tx n/a n/a 10.3 7.1 uart1_dsr/cts n/a n/a n/a n/a uart1_rts/dtr n/a n/a 10.3 7.1 interrupts interface irq00:17 n/a n/a jtag interface tdi n/a n/a async tms n/a n/a async tdo 15.3 10.2 async tck n/a n/a async trst n/a n/a async i/o specificationsall speeds (part 3 of 4) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. pci-x timings are for asynchronous operation up to 133mhz. pc i-x input setup time requirement is 1.2ns for 133mhz and 1.7ns for 66mhz. pci timings (in parentheses) are for asyn chronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. 3. the clock frequency for rmii operation is 50mhz 100ppm. 4. the clock frequency for smii operation is 125mhz 100ppm. 5. these are ddr signals that can change on bo th the positive and negative clock transitions. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum)
440gx ? power pc 440gx embedded processor 72 amcc revision 1.01 ? november 1, 2004 data sheet system interface sysclk n/a n/a n/a n/a tmrclk n/a n/a n/a n/a async sysreset n/a n/a async halt n/a n/a n/a n/a async syserr n/a n/a 10.3 7.1 async testen n/a n/a n/a n/a async drvrinh2 n/a n/a n/a n/a gpio00:31 10.3 7.1 trace interface trcclk n/a n/a 10.3 7.1 trcbs0:2 10.3 7.1 trces0:4 10.3 7.1 trcts0:5 (gpio set) 10.3 7.1 trcts1:5 (ebc set) 15.3 10.2 trcts6 15.3 10.2 i/o specificationsall speeds (part 4 of 4) notes: 1. ethernet interface meets timing requirem ents as defined by ieee 802.3 standard. 2. pci-x timings are for asynchronous operation up to 133mhz. pc i-x input setup time requirement is 1.2ns for 133mhz and 1.7ns for 66mhz. pci timings (in parentheses) are for asyn chronous operation up to 66mhz. pci output hold time requirement is 1ns for 66mhz and 2ns for 33mhz. 3. the clock frequency for rmii operation is 50mhz 100ppm. 4. the clock frequency for smii operation is 125mhz 100ppm. 5. these are ddr signals that can change on bo th the positive and negative clock transitions. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum)
440gx ? power pc 440gx embedded processor amcc 73 revision 1.01 ? november 1, 2004 data sheet i/o specifications500mhzC800mhz notes: 1. perclk rising edge at package pin with a 10pf load tr ails the internal plb clock by approximately 1.3ns. signal input (ns) output (ns) output current (ma) clock notes setup time (t is min) hold time (t ih min) valid delay (t ov max) hold time (t oh min) i/o h (minimum) i/o l (minimum) external slave peripheral interface perdata00:31 2.8 1 6.6 0 15.3 10.2 perclk peraddr00:31 2.9 1 6.6 0 15.3 10.2 perclk perpar0:3 2.7 1 6.0 0 15.3 10.2 perclk perwbe0:3 1.8 1 5.1 0 15.3 10.2 perclk percs0:7 n/a n/a 5.8 0 15.3 10.2 perclk peroe n/a n/a 5.5 0 15.3 10.2 perclk perwe n/a n/a 5.5 0 15.3 10.2 perblast 3.3 1 5.7 n/a 15.3 10.2 perclk perready[rcvrinh] 4.9 1 n/a n/a n/a n/a perclk perr/w 2.5 1 5.7 n/a 15.3 10.2 perclk dmareq0:3 dc dc n/a n/a n/a n/a perclk dmaack0:3 n/a n/a 6.0 0 5.1 6.8 perclk eot0:3/tc0:3 dc dc 6.3 0 15.3 10.2 perclk external master peripheral interface perclk n/a n/a n/a n/a 15.3 10.2 plb clk 1 extreset n/a n/a 6.7 0 15.3 10.2 perclk holdreq 2.8 1 n/a n/a n/a n/a perclk holdack n/a n/a 5.5 0 15.3 10.2 perclk extreq 1.5 1 n/a n/a n/a n/a perclk extack n/a n/a 5.7 0 15.3 10.2 perclk busreq n/a n/a 5.7 0 15.3 10.2 perclk pererr 2.5 1 n/a n/a 15.3 10.2 perclk
440gx ? power pc 440gx embedded processor 74 amcc revision 1.01 ? november 1, 2004 data sheet ddr sdram i/o specifications the ddr sdram controller times its oper ation with internal plb clock signals and generates memclkout0 from the plb clock. the plb clock is an internal signal that cannot be directly observed . however memclkout0 is the same frequency as the plb clock signal and is in phase with the plb clock signal. note: memclkout0 can be advanced with respect to the plb clock by means of the sdram0_clktr program- ming register. in a typical system, users advance memclkout by 90 . this depends on the specific applica- tion and requires a thorough understanding of the memory system in general (refer to the ddr sdram controller chapter in the powerpc 440gx user?s manual ). in the following sections, the label memclkout0(0) refers to memclkout0 when it has not been phase-shifted, and memclkout0(90) refers to memclkout0 when it has been phase-advanced 90 . advancing memclkout0 by 90 creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to memclkout0(90). the rising edge of memclkout0(90) aligns with the first rising edge of the dqs signal. the following ddr data is generated by means of simulation and includes logic, driver, package rlc, and lengths. values are calculated over best case and worst case processes with speed, temperature, and voltage as follows: best case = fast process, -40 c, +1.6v worst case = slow process, +85 c, +1.4v note: in all the following ddr tables and timing diagrams, minimum values are measured under best case condi- tions and maximum values are measured under worst case conditions. the signals are terminated as indicated in the figure below for the ddr timing data in the following sections. ddr sdram signal termination 10pf 10pf memclkout0 memclkout0 120 ? 50 ? addr/ctrl/data/dqs v tt = v dd /2 ppc440gx 30pf
440gx ? power pc 440gx embedded processor amcc 75 revision 1.01 ? november 1, 2004 data sheet ddr sdram output dr iver specifications signal path output current (ma) i/o h (maximum) i/o l (minimum) write data memdata00:07 15.2 15.2 memdata08:15 15.2 15.2 memdata16:23 15.2 15.2 memdata24:31 15.2 15.2 memdata32:39 15.2 15.2 memdata40:47 15.2 15.2 memdata48:55 15.2 15.2 memdata56:63 15.2 15.2 ecc0:7 15.2 15.2 dm0:8 15.2 15.2 memclkout0 15.2 15.2 memaddr00:12 15.2 15.2 ba0:1 15.2 15.2 ras 15.2 15.2 cas 15.2 15.2 we 15.2 15.2 banksel0:3 15.2 15.2 clken0:3 15.2 15.2 dqs0:8 15.2 15.2
440gx ? power pc 440gx embedded processor 76 amcc revision 1.01 ? november 1, 2004 data sheet ddr sdram writ e operation the following diagram illustrates the relationship among the signals in volved with a ddr write operation. ddr sdram write cycle timing dqs memdata plb clk memclkout0 memclkout0(90) addr/cmd t sk t sa t ha t ds t ds t sd t hd t sd t hd t sa = setup time for address and command signals to memclkout0(90) t sk = delay from rising edge of memclkout0(0) to rising/falling edge of signal (skew) t ha = hold time for address and command signals from memclkout0(90) t ds = delay from rising/falling edge of clock to the rising/falling edge of dqs t sd = setup time for data signals (minimum time data is valid before rising/falling edge of dsq) t hd = hold time for data signals (minimum time data is valid after rising/falling edge of dsq)
440gx ? power pc 440gx embedded processor amcc 77 revision 1.01 ? november 1, 2004 data sheet i/o timingddr sdram t ds notes: 1. all of the dqs signals are referenced to memclkout0(0). 2. clock speed is 166mhz. 3. the t ds values in the table incl ude 3/4 of a cycle at 166mhz (6ns x 0.75 = 4.5 ns). 4. to obtain adjusted values for lower clock frequencies, subtract 4.5 ns from the values in the table and add 3/4 of the cycle time for the lower clock frequency (t ds - 4.5 + 0.75t cyc ). signal name t ds (ns) minimum maximum dqs0 4.902 5.601 dqs1 4.872 5.535 dqs2 4.842 5.511 dqs3 4.855 5.546 dqs4 4.832 5.504 dqs5 4.867 5.525 dqs6 4.825 5.488 dqs7 4.880 5.543 dqs8 4.826 5.484 i/o timingddr sdram t sk , t sa , and t ha notes: 1. clock speed is 166mhz. t sk is referenced to memclkout0(0). t sa and t ha are referenced to memclkout0(90). 2. to obtain adjusted t sa values for lower clock frequencies, use 3/4 of the cy cle time for the lower clock frequency and subtract t sk maximum (0.75t cyc - t sk max). 3. to obtain adjusted t ha values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add t sk minimum (0.25t cyc + t sk min). signal name t sk (ns) t sa (ns) t ha (ns) minimum maximum minimum minimum memaddr00:12 0.184 0.592 3.908 1.684 ba0:1 0.439 0.683 3.817 1.939 banksel0:3 0.249 0.779 3.721 1.749 clken0:3 0.344 0.724 3.776 1.844 cas 0.319 0.561 3.939 1.819 ras 0.373 0.683 3.817 1.873 we 0.393 0.639 3.816 1.893
440gx ? power pc 440gx embedded processor 78 amcc revision 1.01 ? november 1, 2004 data sheet ddr sdram read operation the following examples of timing for ddr sdram read operations are based on the relationship between the incoming data and the plb clock signal. since the plb clock cannot be directly observed, the delay of memclkout(0) relative to the plb clock (t md ) is provided. the internal read clock signal, like memclkout0, is deriv ed from the plb clock and can be delayed relative to the plb clock by programming the rdct and rdcd fields in the sdram0_tr1 regi ster. the delay can be programmed from 0 to 1/2 cycle in st eps using rdct. setting rdcd results in a 1/2 cycle delay plus the value set in rdct. the delay of read clock relative to the plb clock (t rd ) shown below assumes the programmable read clock delay is set to zero. ddr sdram memclkout0 and read clock delay i/o timingddr sdram t sd and t hd notes: 1. t sd and t hd are measured under worst case conditions. 2. clock speed for the values in the table is 166mhz. 3. the time values in the table include 1/ 4 of a cycle at 166mhz (6ns x 0.25 = 1.5 ns). 4. to obtain adjusted t sd and t hd values for lower clock frequencies, subtract 1. 5 ns from the values in the table and add 1/4 of the cycle time for the lower clock frequency (e.g., t sd - 1.5 + 0.25t cyc ). signal names reference signal t sd (ns) t hd (ns) memdata00:07, dm0 dqs0 1.240 1.224 memdata08:15, dm1 dqs1 1.236 1.188 memdata16:23, dm2 dqs2 1.223 1.224 memdata24:31, dm3 dqs3 1.221 1.185 memdata32:39, dm4 dqs4 1.238 1.230 memdata40:47, dm5 dqs5 1.286 1.175 memdata48:55, dm6 dqs6 1.234 1.214 memdata56:63, dm7 dqs7 1.257 1.154 ecc0:7, dm8 dqs8 1.237 1.243 read clock plb clk memclkout0(0) t md t rd t md min = t md max = t rd min = t rd max = 567ps 1705ps 183ps -6ps
440gx ? power pc 440gx embedded processor amcc 79 revision 1.01 ? november 1, 2004 data sheet in operation, following the receipt of an address and read command from the ppc440gx, the sdram generates data and the dqs signals coincident with memclkout0. the data is latched into the ppc440gx using a dqs signal that is delayed 1/4 of a cycle. in order to acco mmodate timing variations introduced by the system designs using this chip, the three-st age data path shown below is used to elimin ate metastability and a llow data sampling to be adjusted for minimum latency. this adjustment requires programming the read clock delay and the selection of stage 1, stage 2, or stage 3 data for sampling at rdsp. ddr sdram read data path in the following examples, the data strobes (dqs) and the data are shown to be coincident. there is actually a slight skew as specified by the sdram specifications, an d there can be additional skew due to loading and signal routing. it is recommended that the signal length for all of the eight dqs signals be matched. i/o timingddr sdram t sin and t din notes: 1. t sin = delay from dqs at package pin to c on stage 1 ff. 2. t din = delay from data at package pin to d on stage 1 ff. 3. clock speed for the values in the table is 166mhz. 4. the time values for t sin include 1/4 of a cycle at 166mhz (6ns x 0.25 = 1.5 ns). signal name t sin (ns) minimum t sin (ns) maximum signal name t din (ns) minimum t din (ns) maximum dqs0 2.132 2.884 memdata00:07 0.779 1.502 dqs1 2.132 2.867 memdata08:151 0.789 1.521 dqs2 2.127 2.873 memdata16:23 0.779 1.530 dqs3 2.116 2.851 memdata24:31 0.791 1.553 dqs4 2.100 2.845 memdata32:39 0.766 1.501 dqs5 2.103 2.844 memdata40:47 0.754 1.525 dqs6 2.144 2.902 memdata48:55 0.747 1.513 dqs7 2.110 2.864 memdata56:63 0.770 1.521 dqs8 2.122 2.860 ecc0:7 0.759 1.464 stage 1 stage 2 stage 3 rdsp plb bus ff, ff ff ff data read select (sdram0_tr1) dqs 1/4 cycle delay plb clock programmed delay d c package pins mux read clock c c c d d d ff timing: t is = input setup time = 0.2ns t ih = input hold time = 0.1ns t p = propagation delay (d to q or c to q) = xl ecc ff: flip-flop xl: transparent latch q q q q 0.4ns maximum
440gx ? power pc 440gx embedded processor 80 amcc revision 1.01 ? november 1, 2004 data sheet example 1: if the data-to-plb clock timing is as shown in the exampl e below, then the read clock is not delayed and the stage 1 data is sampled at (1) . except for small, low frequency memory s ystems with the memory located physically close to the ppc440gx, it is unlikely that stage 1 data can be sampled. when the data comes later, it is necessary to sample stage 2 or stage 3 data. (see examples 2 and 3). another way to get the desired data-to-plb timing to allow stage 1 sampling is to buffer memclkout0 and skew it enough to guarantee the timing. in this example t t = 1.27ns at worst case conditions. ddr sdram read cycle timingexample 1 dqs at pin plb clock t sin t din = delay from data at package pin to d on stage 1 ff. t sin = delay from dqs at package pin to c on stage 1 ff. data at pin d0 d1 d2 d3 dqs stage 1 c d0 d1 d2 d3 t din d0 d2 data in stage 1 d d1 d3 data out stage 1 high low t p d0 d2 d1 d3 data in at rdsp high low with no ecc t t t p = propagation delay through ffs t t = propagation delay, stage 1 input to rdsp input w/o ecc d0 d2 d1 d3 data out rdsp high low (1) d2 d2 t p d0 d0
440gx ? power pc 440gx embedded processor amcc 81 revision 1.01 ? november 1, 2004 data sheet example 2: in this example read clock is delayed almost 1/2 cycle. without ecc, stage 2 data can be sampled at (2) . if ecc is enabled, stage 3 data must be sample d (see example 3). in this example, t t = 1.27ns and t te = 3.589ns at worst case conditions. ddr sdram read cycle timingexample 2 example 3: in this example, ecc is enabled. this requires that stage 3 data be sampled at (3) . if ecc is disabled, the system dqs at pin plb clock read clock delayed t sin data at pin d0 d1 d2 d3 dqs stage 1 c d0 d1 d2 d3 t din d0 d2 data in stage 1 d d1 d3 data out stage 1 high low t p d0 d2 d1 d3 data in at rdsp high low without ecc t t = propagation delay from stage 2 input to rdsp input w/o ecc d0 d2 d1 d3 data out stage 2 high low data out at rdsp high low (2) without ecc t p d0 d2 d1 d3 data in at rdsp high low with ecc d0 d2 d1 d3 t te = propagation delay from stage 2 input to rdsp input with ecc t t t te d0 d2
440gx ? power pc 440gx embedded processor 82 amcc revision 1.01 ? november 1, 2004 data sheet will still work, but there will be more latency befo re the data is sample d into rdsp. again, t t = 1.27ns and t te = 3.589ns at worst case conditions. ddr sdram read cycle timingexample 3 dqs at pin plb clock read clock delayed t sin data at pin d0 d1 d2 d3 dqs stage 1 c d0 d1 d2 d3 t din d0 d2 data in stage 1 d d1 d3 data out stage 1 high low t p d0 d2 d1 d3 data out stage 3 high low with ecc t t = propagation delay from stage 2 input to rdsp input w/o ecc d0 d2 d1 d3 data out stage 2 high low data out rdsp high low (3) with ecc t p d0 d2 d1 d3 data in at rdsp high low with ecc d0 d2 d1 d3 t te = propagation delay from stage 2 input to rdsp input with ecc t te d0 d2
440gx ? power pc 440gx embedded processor amcc 83 revision 1.01 ? november 1, 2004 data sheet initialization the ppc440gx provides the option for setting initial parameters based on default values or by reading them from a slave prom attached to the iic0 bus (see eeprom below). some of th e default values ca n be altered by strapping on external pins (see strapping below). strapping while the sysreset input pin is low (system reset), the state of certain i/o pins is read to enable certain default initial conditions prior to ppc440gx start-up. the actual capture instant is the nearest sysclk edge before the deassertion of reset. these pins must be strapped using external pull-up (logical 1) or pull-down (logical 0) resistors to select the desired default conditions. they are used for strap functions only during reset. following reset they are used for normal functions. the following table lists the strapping pins along with their functions and strapping options: eeprom during reset, initial conditions other than those obtained from the strapping pins can be read from a rom device connected to the iic0 port. at the de-assertion of sysreset, if the bootstrap controller is enabled, the ppc440gx sequentially reads 16 bytes from the rom device on the iic0 port and uses the first 8 bytes to set the sdr0_strp0 and sdr0_strp1 registers accordingly. othe rwise, the default values set in the cpr0 and sdr0 registers are used for initialization. the initialization settings and their default values are covered in detail in the powerpc 440gx embedded processor user?s manual . strapping pin assignments function option ball strapping v24 (uart0_dcd ) v02 (uart0_dsr ) l07 (gmc1txer) serial device is disabled. ea ch of the four options (aC d) is a combination of boot source, boot-source width, and clock frequency specificat ions. refer to the iic bootstrap controller chapter in the ppc440gx embedded processor user?s manual for details. a 000 b0x1 c 010 d 100 serial device is enabled. the option being selected is the iic0 slave address that will respond with strapping data. 0x54 1 0 1 0x50 1 1 1
440gx ? power pc 440gx embedded processor 84 amcc revision 1.01 ? november 1, 2004 data sheet revision log date contents of modification 08/07/2002 add revision log. 08/30/2002 change emc0:1txd0:1 and emc0:1txen t ov from 15 to 11 ns. 09/25/2002 update for l2 cache 10/22/2002 add heat sink mounting information . 11/20/2002 update i/o timing data. 01/07/2003 update pci-x i/o voltage specification. correct package drawing 01/22/2003 correct description of sysreset signal. update for 533mhz parts and add power supply current values. 03/25/2003 update ddr sdram timing. change rtbixtx and rx control signals to data signals. 06/16/2003 add 667mhz part numbers, update i/o specif ications, and fill in missing data points. 07/15/2003 update information concerning higher s peed parts, bus clock rati os, the duplicate trace signals, and initialization strapping pins. update ethernet signals with new and moved signals. 07/17/2003 remove ibm confidential. 12/02/2003 revise ddr sdram i/o section. 01/13/2004 correct trcts6 signal data (pin assignment and multiplexing). 02/12/2004 restore v dd /ov dd voltage sequence restriction. 02/25/2004 add three revision c part numbers. 03/04/2004 update part number list. update dimensions on package drawing. 03/25/2004 correct gmctxclk signal des cription from input-only to i/o. 05/12/2004 add plastic package data, new power data, and update part number list. 05/20/2004 upgrade 533mhz ceramic part to 105 c rating. 06/15/2004 correct dimensions on ceramic package drawing. 06/30/2004 replace misssing 533mhz c temperature range part. 11/01/2004 add information on minimum sysclk and trst duration during power-on reset. remove power sequence restrictions not e from absolute maximum rating table. restate power sequencing restrictions in recommended dc operating conditions table. convert to amcc format.
440gx ? power pc 440gx embedded processor amcc 85 revision 1.01 ? november 1, 2004 data sheet printed in the united states of america, november 2004 the following are trademarks of amcc in the united states, or other countries, or both: other company, product, and service names may be trademarks or service marks of others. the information contained in this document is subject to change or withdrawal at any time without notice and is being provided on an "as is" basis without wa rranty or indemnity of an y kind, whether express or implied, including without limitation, the implied warranties of non-infrin gement, merchantability, or fitness for a particular purpose. any produc ts, services, or programs discussed in this document are sold or licensed under amcc's standard terms and conditions, copies of which may be obtained from your local amcc representative. nothing in this document shall ope rate as an express or implied license or indemnity under the intellectual property ri ghts of amcc or third parties. without limiting the generality of the foregoing, an y performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal amcc test. therefore, the results obtained in other operating environments may vary significantly. unde r no circumstances will amcc be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein. amcc
440gx ? power pc 440gx embedded processor 86 amcc revision 1.01 ? november 1, 2004 data sheet applied micro circuits corporation 6290 sequence dr., san diego, ca 92121 phone: (858) 450-9333 ? (800) 755-2622 ? fax: (858) 450-9885 http://www.amcc.com amcc reserves the right to make changes to its products, its datasheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially co mply with the latest available datasheet. please consult amcc?s term and condi tions of sale for its warranties and ot her terms, conditions and limitations. amcc may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the info rmation is current. amcc does not assume any lia - bility arising out of the application or use of any product or circuit described herein, neither does it convey any license und er its patent rights nor the rights of others. amcc reserves the ri ght to ship devices of higher grade in place of those of lower grade. amcc semiconductor products are not designed , intended, authorized, or warranted to be suitable for use in life-support applications, devices or systems or other critical applications. amcc is a registered trademark of appli ed micro circuits corporation. copyright ? 2004 applied micro circuits corporation.

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